Morphological image processing on VLSI opto-electronic array processors

Wai Chi Fang, Timothy Shaw, Jeffrey Yu

研究成果: Conference contribution同行評審

摘要

A full-custom op to-electronic VLSI design for high-speed morphological image processing has been developed by combining a 2- dimensional fine-grain parallel array architecture with on-chip focalplane photodetectors and transmitters. The processor array performs morphological functions on the opto-detected binary image with a programmable structuring element of any size. A specific language called MIPL is defined for morphological image processing and fully supported by the MIP hardware. Sophisticated morphological image processing algorithms were implemented by executing specific parallel programs (written in MIPL) on the MIP. An 8x8 array processor prototype chip has been designed in 1.2 mm × 1.2 mm silicon area using the MOSIS 2-μm CMOS process.

原文English
主出版物標題Workshop on VLSI Signal Processing 1992
編輯Wojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
發行者Institute of Electrical and Electronics Engineers Inc.
頁面277-286
頁數10
ISBN(電子)0780308115, 9780780308114
DOIs
出版狀態Published - 1 一月 1992
事件6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States
持續時間: 28 十月 199230 十月 1992

出版系列

名字Workshop on VLSI Signal Processing 1992

Conference

Conference6th IEEE Workshop on VLSI Signal Processing
國家/地區United States
城市Los Angeles
期間28/10/9230/10/92

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