A full-custom op to-electronic VLSI design for high-speed morphological image processing has been developed by combining a 2- dimensional fine-grain parallel array architecture with on-chip focalplane photodetectors and transmitters. The processor array performs morphological functions on the opto-detected binary image with a programmable structuring element of any size. A specific language called MIPL is defined for morphological image processing and fully supported by the MIP hardware. Sophisticated morphological image processing algorithms were implemented by executing specific parallel programs (written in MIPL) on the MIP. An 8x8 array processor prototype chip has been designed in 1.2 mm × 1.2 mm silicon area using the MOSIS 2-μm CMOS process.