More effective power-gated circuit optimization with multi-bit retention registers

Shu Hung Lin*, Po-Hung Lin

*此作品的通信作者

研究成果: Conference contribution同行評審

6 引文 斯高帕斯(Scopus)

摘要

Applying retention registers is one of the most effective and efficient approaches to keep flip-flop states in power-gated circuits during the sleep mode. Instead of replacing each flip-flop in a power-gated circuit with a single-bit retention register (SBRR), recent research has shown that applying multi-bit retention registers (MBRRs) can effectively reduce the storage size, and hence save more chip area and leakage power. However, the previous work simply adopted greedy heuristics for power-gated circuit optimization with MBRRs, which first break feedback paths and then iteratively replace a flip-flop covering the maximum number of (k-1)-link paths with a k-bit retention register. Different from the previous work, this paper presents an even more effective approach based on integer-linear-programming (ILP) formulation with simultaneous consideration of all feedback paths. Experimental results show that the proposed approach can further reduce up to 46% storage size compared with the previous work.

原文English
主出版物標題2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - Digest of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
頁面213-217
頁數5
2015-January
版本January
ISBN(電子)9781479962785
DOIs
出版狀態Published - 5 一月 2015
事件2014 33rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - San Jose, United States
持續時間: 2 十一月 20146 十一月 2014

出版系列

名字IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
發行者Institute of Electrical and Electronics Engineers Inc.
ISSN(列印)1092-3152

Conference

Conference2014 33rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014
國家/地區United States
城市San Jose
期間2/11/146/11/14

指紋

深入研究「More effective power-gated circuit optimization with multi-bit retention registers」主題。共同形成了獨特的指紋。

引用此