Monolithic microprocessor and RF transceiver in 0.25-micron FDSOI CMOS

E. McShane*, K. Shenai, L. Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi  Fang

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

A monolithic RFIC in 0.25-micron fully-depleted SOI CMOS has been designed consisting of a microcoded 8-bit 33-MHz microprocessor, a 400-MHz 8-bit ASK-modulated RF transceiver, and two integrated dc-dc voltage converters for power management. This architecture exploits a low-power (sub 2-V) digital process for mixed-signal VLSI in a die size measuring 2.2 mm × 2.2 mm.

原文English
主出版物標題Proceedings of the IEEE Great Lakes Symposium on VLSI
發行者IEEE
頁面332-333
頁數2
ISBN(列印)0769501044
DOIs
出版狀態Published - 1999
事件Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA
持續時間: 4 3月 19996 3月 1999

出版系列

名字Proceedings of the IEEE Great Lakes Symposium on VLSI
ISSN(列印)1066-1395

Conference

ConferenceProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
城市Ann Arbor, MI, USA
期間4/03/996/03/99

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