Monolithic low noise and low zero-g offset CMOS/MEMS accelerometer readout scheme

Yu Sian Liu; Kuei-Ann Wen

doi:10.3390/mi9120637

Monolithic low noise and low zero-g offset CMOS/MEMS accelerometer readout scheme

Yu Sian Liu^*, Kuei-Ann Wen

^*此作品的通信作者

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

摘要

A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/ √ Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.

原文	English
文章編號	637
期刊	Micromachines
卷	9
發行號	12
DOIs	https://doi.org/10.3390/mi9120637
出版狀態	Published - 30 11月 2018

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10.3390/mi9120637

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@article{a829b51d8dc741868876a30f773c4ea2,

title = "Monolithic low noise and low zero-g offset CMOS/MEMS accelerometer readout scheme",

abstract = "A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/ √ Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.",

keywords = "Accelerometer readout, Low noise, Low zero-g offset",

author = "Liu, {Yu Sian} and Kuei-Ann Wen",

year = "2018",

month = nov,

day = "30",

doi = "10.3390/mi9120637",

language = "English",

volume = "9",

journal = "Micromachines",

issn = "2072-666X",

publisher = "Multidisciplinary Digital Publishing Institute (MDPI)",

number = "12",

}

TY - JOUR

T1 - Monolithic low noise and low zero-g offset CMOS/MEMS accelerometer readout scheme

AU - Liu, Yu Sian

AU - Wen, Kuei-Ann

PY - 2018/11/30

Y1 - 2018/11/30

N2 - A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/ √ Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.

AB - A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/ √ Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.

KW - Accelerometer readout

KW - Low noise

KW - Low zero-g offset

UR - http://www.scopus.com/inward/record.url?scp=85057790714&partnerID=8YFLogxK

U2 - 10.3390/mi9120637

DO - 10.3390/mi9120637

M3 - Article

AN - SCOPUS:85057790714

SN - 2072-666X

VL - 9

JO - Micromachines

JF - Micromachines

IS - 12

M1 - 637

ER -

Monolithic low noise and low zero-g offset CMOS/MEMS accelerometer readout scheme

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