Monolithic low noise and low zero-g offset CMOS/MEMS accelerometer readout scheme

Yu Sian Liu*, Kuei-Ann Wen

*此作品的通信作者

    研究成果: Article同行評審

    5 引文 斯高帕斯(Scopus)

    摘要

    A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/ √ Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.

    原文English
    文章編號637
    期刊Micromachines
    9
    發行號12
    DOIs
    出版狀態Published - 30 11月 2018

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