@inproceedings{b878550284794ae886c240120ed55696,
title = "Monolithic 3D Integration of 2D Electronics based on Two-Dimensional Solid-Phase Crystallization",
abstract = "Monolithic 3D integration (M3D) of two-dimensional materials (2DMs) based on a device structure similar to the vertically stacked nanosheet (NS) gate-all-around (GAA) field-effect transistor (NS-GAAFET) is one of the most feasible paths for end-of-roadmap logic device scaling. A novel synthesis route, 2D solid-phase crystallization (2DSPC), is presented in this paper for M3D of 2DMs. 2DSPC presents a unique opportunity for achieving wafer-level uniformity, centimeter-scale monocrystalline grain, and scalable synthesis for multiple vertical layers. We believe 2DSPC offers a promising pathway toward future cost-effective M3D-2D electronics.",
author = "Lin, {Chih Pin} and Kang, {Yu Wei} and Hsu, {Chih Pin} and Hsu, {Hao Hua} and Huang, {Jyun Hong} and Chen, {Rui Fu} and Wu, {Chien Tin} and Lee, {Yao Jen} and Tuo-Hung Hou",
note = "Publisher Copyright: {\textcopyright} 2021 JSAP; 41st Symposium on VLSI Technology, VLSI Technology 2021 ; Conference date: 13-06-2021 Through 19-06-2021",
year = "2021",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 Symposium on VLSI Technology, VLSI Technology 2021",
address = "美國",
}