Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM

Chang Hong Shen; Jia Min Shieh; Tsung Ta Wu; Wen Hsien Huang; Chih Chao Yang; Chih Jen Wan; Chein Din Lin; Hsing Hsiang Wang; Bo Yuan Chen; Guo Wei Huang; Yu Chung Lien; Simon Wong; Chieh Wang; Yin-Chieh Lai; Chien Fu Chen; Meng Fan Chang; Chen-Ming Hu; Fu Liang Yang

doi:10.1109/IEDM.2013.6724593

Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM

Chang Hong Shen, Jia Min Shieh, Tsung Ta Wu, Wen Hsien Huang, Chih Chao Yang, Chih Jen Wan, Chein Din Lin, Hsing Hsiang Wang, Bo Yuan Chen, Guo Wei Huang, Yu Chung Lien, Simon Wong, Chieh Wang, Yin-Chieh Lai, Chien Fu Chen, Meng Fan Chang, Chen-Ming Hu, Fu Liang Yang

研究成果: Conference contribution › 同行評審

30 引文斯高帕斯（Scopus）

摘要

For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.

原文	English
主出版物標題	2013 IEEE International Electron Devices Meeting, IEDM 2013
頁面	9.3.1-9.3.4
DOIs	https://doi.org/10.1109/IEDM.2013.6724593
出版狀態	Published - 2013
事件	2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, 美國持續時間: 9 12月 2013 → 11 12月 2013

出版系列

名字	Technical Digest - International Electron Devices Meeting, IEDM
ISSN（列印）	0163-1918

Conference

Conference	2013 IEEE International Electron Devices Meeting, IEDM 2013
國家/地區	美國
城市	Washington, DC
期間	9/12/13 → 11/12/13

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10.1109/IEDM.2013.6724593

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Link to publication in Scopus

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Shen, C. H., Shieh, J. M., Wu, T. T., Huang, W. H., Yang, C. C., Wan, C. J., Lin, C. D., Wang, H. H., Chen, B. Y., Huang, G. W., Lien, Y. C., Wong, S., Wang, C., Lai, Y.-C., Chen, C. F., Chang, M. F., Hu, C.-M., & Yang, F. L. (2013). Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM. 於 2013 IEEE International Electron Devices Meeting, IEDM 2013 (頁 9.3.1-9.3.4). 文章 6724593 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2013.6724593

@inproceedings{042791aab38d45c8b8ff0461e285a825,

title = "Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM",

abstract = "For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.",

author = "Shen, {Chang Hong} and Shieh, {Jia Min} and Wu, {Tsung Ta} and Huang, {Wen Hsien} and Yang, {Chih Chao} and Wan, {Chih Jen} and Lin, {Chein Din} and Wang, {Hsing Hsiang} and Chen, {Bo Yuan} and Huang, {Guo Wei} and Lien, {Yu Chung} and Simon Wong and Chieh Wang and Yin-Chieh Lai and Chen, {Chien Fu} and Chang, {Meng Fan} and Chen-Ming Hu and Yang, {Fu Liang}",

year = "2013",

doi = "10.1109/IEDM.2013.6724593",

language = "English",

isbn = "9781479923076",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

pages = "9.3.1--9.3.4",

booktitle = "2013 IEEE International Electron Devices Meeting, IEDM 2013",

note = "2013 IEEE International Electron Devices Meeting, IEDM 2013 ; Conference date: 09-12-2013 Through 11-12-2013",

}

Shen, CH, Shieh, JM, Wu, TT, Huang, WH, Yang, CC, Wan, CJ, Lin, CD, Wang, HH, Chen, BY, Huang, GW, Lien, YC, Wong, S, Wang, C, Lai, Y-C, Chen, CF, Chang, MF, Hu, C-M & Yang, FL 2013, Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM. 於 2013 IEEE International Electron Devices Meeting, IEDM 2013., 6724593, Technical Digest - International Electron Devices Meeting, IEDM, 頁 9.3.1-9.3.4, 2013 IEEE International Electron Devices Meeting, IEDM 2013, Washington, DC, 美國, 9/12/13. https://doi.org/10.1109/IEDM.2013.6724593

TY - GEN

T1 - Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM

AU - Shen, Chang Hong

AU - Shieh, Jia Min

AU - Wu, Tsung Ta

AU - Huang, Wen Hsien

AU - Yang, Chih Chao

AU - Wan, Chih Jen

AU - Lin, Chein Din

AU - Wang, Hsing Hsiang

AU - Chen, Bo Yuan

AU - Huang, Guo Wei

AU - Lien, Yu Chung

AU - Wong, Simon

AU - Wang, Chieh

AU - Lai, Yin-Chieh

AU - Chen, Chien Fu

AU - Chang, Meng Fan

AU - Hu, Chen-Ming

AU - Yang, Fu Liang

PY - 2013

Y1 - 2013

N2 - For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.

AB - For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.

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U2 - 10.1109/IEDM.2013.6724593

DO - 10.1109/IEDM.2013.6724593

M3 - Conference contribution

AN - SCOPUS:84894362613

SN - 9781479923076

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 9.3.1-9.3.4

BT - 2013 IEEE International Electron Devices Meeting, IEDM 2013

T2 - 2013 IEEE International Electron Devices Meeting, IEDM 2013

Y2 - 9 December 2013 through 11 December 2013

ER -

Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM

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