摘要
An analytical model for switch-induced error voltage on a switched capacitor is derived. A compact expression contains the effects of gate voltage falling rate, threshold voltage, and storage capacitance. It can be used to quickly predict the error voltage. The model is in good agreement with computer simulations using SPICE program and experiment.
| 原文 | English |
|---|---|
| 頁（從 - 到） | 911-913 |
| 頁數 | 3 |
| 期刊 | IEEE transactions on circuits and systems |
| 卷 | 30 |
| 發行號 | 12 |
| DOIs | |
| 出版狀態 | Published - 1 1月 1983 |