Modeling the Impurity Profile in an Ion-Implanted Layer of an IGFET for the Calculation of Threshold Voltages

Luong Mo Dang; Hiroshi Iwai

doi:10.1109/T-ED.1981.20291

Modeling the Impurity Profile in an Ion-Implanted Layer of an IGFET for the Calculation of Threshold Voltages

Luong Mo Dang, Hiroshi Iwai

國際半導體產業學院

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

An extremely simple model for the impurity profile in an ion-implanted channel layer of an IGFET is applied to simulating the substrate bias dependence of its threshold voltage. Excellent agreement is obtained between theory and experiment on n-channel silicon devices.

原文	English
頁（從 - 到）	116-117
頁數	2
期刊	IEEE Transactions on Electron Devices
卷	28
發行號	1
DOIs	https://doi.org/10.1109/T-ED.1981.20291
出版狀態	Published - 1月 1981

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10.1109/T-ED.1981.20291

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abstract = "An extremely simple model for the impurity profile in an ion-implanted channel layer of an IGFET is applied to simulating the substrate bias dependence of its threshold voltage. Excellent agreement is obtained between theory and experiment on n-channel silicon devices.",

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Modeling the Impurity Profile in an Ion-Implanted Layer of an IGFET for the Calculation of Threshold Voltages

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