Modeling the Impurity Profile in an Ion-Implanted Layer of an IGFET for the Calculation of Threshold Voltages

Luong Mo Dang; Hiroshi Iwai

doi:10.1109/T-ED.1981.20291

Modeling the Impurity Profile in an Ion-Implanted Layer of an IGFET for the Calculation of Threshold Voltages

Luong Mo Dang, Hiroshi Iwai

國際半導體產業學院

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

An extremely simple model for the impurity profile in an ion-implanted channel layer of an IGFET is applied to simulating the substrate bias dependence of its threshold voltage. Excellent agreement is obtained between theory and experiment on n-channel silicon devices.

原文	English
頁（從 - 到）	116-117
頁數	2
期刊	IEEE Transactions on Electron Devices
卷	28
發行號	1
DOIs	https://doi.org/10.1109/T-ED.1981.20291
出版狀態	Published - 1月 1981

存取文件

10.1109/T-ED.1981.20291

其它文件與鏈接

Link to publication in Scopus

引用此

@article{e68b4bc62e42436fb47e2c373a81d8c8,

title = "Modeling the Impurity Profile in an Ion-Implanted Layer of an IGFET for the Calculation of Threshold Voltages",

abstract = "An extremely simple model for the impurity profile in an ion-implanted channel layer of an IGFET is applied to simulating the substrate bias dependence of its threshold voltage. Excellent agreement is obtained between theory and experiment on n-channel silicon devices.",

author = "Dang, {Luong Mo} and Hiroshi Iwai",

year = "1981",

month = jan,

doi = "10.1109/T-ED.1981.20291",

language = "English",

volume = "28",

pages = "116--117",

journal = "Ieee Transactions On Electron Devices",

issn = "0018-9383",

publisher = "IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",

number = "1",

}

TY - JOUR

T1 - Modeling the Impurity Profile in an Ion-Implanted Layer of an IGFET for the Calculation of Threshold Voltages

AU - Dang, Luong Mo

AU - Iwai, Hiroshi

PY - 1981/1

Y1 - 1981/1

N2 - An extremely simple model for the impurity profile in an ion-implanted channel layer of an IGFET is applied to simulating the substrate bias dependence of its threshold voltage. Excellent agreement is obtained between theory and experiment on n-channel silicon devices.

AB - An extremely simple model for the impurity profile in an ion-implanted channel layer of an IGFET is applied to simulating the substrate bias dependence of its threshold voltage. Excellent agreement is obtained between theory and experiment on n-channel silicon devices.

UR - http://www.scopus.com/inward/record.url?scp=0019397083&partnerID=8YFLogxK

U2 - 10.1109/T-ED.1981.20291

DO - 10.1109/T-ED.1981.20291

M3 - Article

AN - SCOPUS:0019397083

SN - 0018-9383

VL - 28

SP - 116

EP - 117

JO - Ieee Transactions On Electron Devices

JF - Ieee Transactions On Electron Devices

IS - 1

ER -

Modeling the Impurity Profile in an Ion-Implanted Layer of an IGFET for the Calculation of Threshold Voltages

摘要

存取文件

其它文件與鏈接

指紋

引用此