TY - JOUR
T1 - Modeling the impact of back-end process variation on circuit performance
AU - Sylvester, Dennis
AU - Nakagawa, O. Sam
AU - Hu, Chen-Ming
PY - 1999
Y1 - 1999
N2 - We present a stochastic approach to account for on-chip interconnect process variation. A Monte Carlo approach is taken using actual process distributions to generate realistic 3-σ performance corners. Accurate analytical models are used to provide a >3 order of magnitude speedup over simulation techniques. Resulting delay and noise performance spreads are 33 to 63% tighter than those found using a conventional technique. We apply this method to a clock distribution network to more precisely determine clock skew.
AB - We present a stochastic approach to account for on-chip interconnect process variation. A Monte Carlo approach is taken using actual process distributions to generate realistic 3-σ performance corners. Accurate analytical models are used to provide a >3 order of magnitude speedup over simulation techniques. Resulting delay and noise performance spreads are 33 to 63% tighter than those found using a conventional technique. We apply this method to a clock distribution network to more precisely determine clock skew.
UR - http://www.scopus.com/inward/record.url?scp=0032599268&partnerID=8YFLogxK
U2 - 10.1109/VTSA.1999.785999
DO - 10.1109/VTSA.1999.785999
M3 - Conference article
AN - SCOPUS:0032599268
SN - 1524-766X
SP - 58
EP - 61
JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
T2 - Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications
Y2 - 7 June 1999 through 10 June 1999
ER -