Modeling RF MOSFETs after electrical stress using low-noise microstrip line layout

H. L. Kao; Albert Chin; J. M. Lai; C. F. Lee; K. C. Chiang; S. P. McAlister

doi:10.1109/RFIC.2005.1489616

Modeling RF MOSFETs after electrical stress using low-noise microstrip line layout

H. L. Kao^*, Albert Chin, J. M. Lai, C. F. Lee, K. C. Chiang, S. P. McAlister

^*此作品的通信作者

研究成果: Conference article › 同行評審

17 引文斯高帕斯（Scopus）

摘要

A novel microstrip line layout is developed to direct measure the min. noise figure (NF _min ) accurately instead of the complicated de-embedding procedure in conventional CPW line. Very low NF _min of 1.05 dB at 10 GHz is directly measured in 16 gate fingers 0.18μm MOSFETs without any de-embedding. Based on the accurate NF _min measurement, we have developed the self-consistent DC, S-parameters and NF _min model to predict device characteristics after the continuous stress with good accuracy.

原文	English
文章編號	RMO2C-5
頁（從 - 到）	157-160
頁數	4
期刊	Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium
DOIs	https://doi.org/10.1109/RFIC.2005.1489616
出版狀態	Published - 15 11月 2005
事件	2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium - Digest of Papers - Long Beach, CA, 美國持續時間: 12 6月 2005 → 14 6月 2005

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10.1109/RFIC.2005.1489616

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@article{3a47bb41173a4e3ab173bb792ba5fe00,

title = "Modeling RF MOSFETs after electrical stress using low-noise microstrip line layout",

abstract = " A novel microstrip line layout is developed to direct measure the min. noise figure (NF min ) accurately instead of the complicated de-embedding procedure in conventional CPW line. Very low NF min of 1.05 dB at 10 GHz is directly measured in 16 gate fingers 0.18μm MOSFETs without any de-embedding. Based on the accurate NF min measurement, we have developed the self-consistent DC, S-parameters and NF min model to predict device characteristics after the continuous stress with good accuracy.",

keywords = "Lifetime, Model, NF, RF noise, Stress",

author = "Kao, {H. L.} and Albert Chin and Lai, {J. M.} and Lee, {C. F.} and Chiang, {K. C.} and McAlister, {S. P.}",

year = "2005",

month = nov,

day = "15",

doi = "10.1109/RFIC.2005.1489616",

language = "English",

pages = "157--160",

journal = "Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium",

issn = "1529-2517",

note = "2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium - Digest of Papers ; Conference date: 12-06-2005 Through 14-06-2005",

}

TY - JOUR

T1 - Modeling RF MOSFETs after electrical stress using low-noise microstrip line layout

AU - Kao, H. L.

AU - Chin, Albert

AU - Lai, J. M.

AU - Lee, C. F.

AU - Chiang, K. C.

AU - McAlister, S. P.

PY - 2005/11/15

Y1 - 2005/11/15

N2 - A novel microstrip line layout is developed to direct measure the min. noise figure (NF min ) accurately instead of the complicated de-embedding procedure in conventional CPW line. Very low NF min of 1.05 dB at 10 GHz is directly measured in 16 gate fingers 0.18μm MOSFETs without any de-embedding. Based on the accurate NF min measurement, we have developed the self-consistent DC, S-parameters and NF min model to predict device characteristics after the continuous stress with good accuracy.

AB - A novel microstrip line layout is developed to direct measure the min. noise figure (NF min ) accurately instead of the complicated de-embedding procedure in conventional CPW line. Very low NF min of 1.05 dB at 10 GHz is directly measured in 16 gate fingers 0.18μm MOSFETs without any de-embedding. Based on the accurate NF min measurement, we have developed the self-consistent DC, S-parameters and NF min model to predict device characteristics after the continuous stress with good accuracy.

KW - Lifetime

KW - Model

KW - NF

KW - RF noise

KW - Stress

UR - http://www.scopus.com/inward/record.url?scp=27644575920&partnerID=8YFLogxK

U2 - 10.1109/RFIC.2005.1489616

DO - 10.1109/RFIC.2005.1489616

M3 - Conference article

AN - SCOPUS:27644575920

SN - 1529-2517

SP - 157

EP - 160

JO - Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium

JF - Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium

M1 - RMO2C-5

T2 - 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium - Digest of Papers

Y2 - 12 June 2005 through 14 June 2005

ER -

Modeling RF MOSFETs after electrical stress using low-noise microstrip line layout

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