摘要
Pocket implant is widely used in deep-sub-micron CMOS technologies to combat short channel effects. It, however, brings anomalously large drain-induced threshold voltage shift and low output resistance to long channel devices. This creates a serious problem for high-performance analog circuits. In this paper, the first physical model of these effects are proposed and verified against data from a 0.18μm technology. This model is suitable for SPICE modeling.
原文 | English |
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頁(從 - 到) | 171-174 |
頁數 | 4 |
期刊 | Technical Digest - International Electron Devices Meeting |
DOIs | |
出版狀態 | Published - 1999 |
事件 | 1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA 持續時間: 5 12月 1999 → 8 12月 1999 |