Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling

Wen Chin Lee; Chen-Ming Hu

doi:10.1109/VLSIT.2000.852824

Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling

Wen Chin Lee^*, Chen-Ming Hu

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

120 引文斯高帕斯（Scopus）

摘要

A model is proposed to quantify the tunneling currents through ultra-thin gate oxides. With a proper set of effective mass and barrier height, this new model can accurately predict the gate and substrate currents and all the sub-components in dual-gate CMOS devices. This model can also be employed to extract oxide thickness (T_ox) for thin oxide from I_g-V_g data with 0.1 angstroms sensitivity, where CV extraction can be difficult or impossible.

原文	English
頁（從 - 到）	198-199
頁數	2
期刊	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/VLSIT.2000.852824
出版狀態	Published - 1 1月 2000
事件	2000 Symposium on VLSI Technology - Honolulu, HI, USA 持續時間: 13 6月 2000 → 15 6月 2000

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10.1109/VLSIT.2000.852824

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AB - A model is proposed to quantify the tunneling currents through ultra-thin gate oxides. With a proper set of effective mass and barrier height, this new model can accurately predict the gate and substrate currents and all the sub-components in dual-gate CMOS devices. This model can also be employed to extract oxide thickness (Tox) for thin oxide from Ig-Vg data with 0.1 angstroms sensitivity, where CV extraction can be difficult or impossible.

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JO - Digest of Technical Papers - Symposium on VLSI Technology

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Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling

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