Modeling and minimizing variations of gate-all-around multiple-channel nanowire TFTs

Po Chun Huang, Lu An Chen, C. C. Chen, Jeng-Tzong Sheu*

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this paper we describe the electrical performance of poly-Si gate-all-around (GAA) thin-film transistors (TFTs) featuring multiple-channel nanowires (NWs). To minimize the variation in the electrical characteristics of these TFTs, we compared the effects of several approach, including the use of a multiple-gate structure, the number of multiple channels, and NH 3 plasma treatment. Relative to a tri-gate structure, the GAA devices exhibited superior performance. In addition, the presence of multiple channels efficiently reduced the variation in the electrical characteristics. Devices featuring 16-cnannel present the minimized standard deviation in both threshold voltage and subthreshold swing (30 mV and 11.4 mV/dec, respectively). The device-to-device variation due to random grain-size distribution in poly-Si GAA NW TFT was modeled by Poisson area scatter model. The electrical measurements of poly-Si GAA NW TFTs and the model are in agreement. Finally, NH 3 plasma treatment of the GAA TFTs featuring multiple channels further decreased the electrical variations and improved the device performance.

原文English
主出版物標題2011 11th IEEE International Conference on Nanotechnology, NANO 2011
頁面600-603
頁數4
DOIs
出版狀態Published - 2011
事件2011 11th IEEE International Conference on Nanotechnology, NANO 2011 - Portland, OR, 美國
持續時間: 15 8月 201119 8月 2011

出版系列

名字Proceedings of the IEEE Conference on Nanotechnology
ISSN(列印)1944-9399
ISSN(電子)1944-9380

Conference

Conference2011 11th IEEE International Conference on Nanotechnology, NANO 2011
國家/地區美國
城市Portland, OR
期間15/08/1119/08/11

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