TY - JOUR
T1 - Modeling and formal verification of dataflow graph in system-level design using petri net
AU - Chiang, Tsung Hsi
AU - Dung, Lan-Rong
AU - Yaung, Ming Feng
PY - 2005/12/1
Y1 - 2005/12/1
N2 - Formal verification in system-level, which also means architecture verification, is different from functional verification in RTL level. DSP algorithms need high-level transformation to achieve optimal goals before mapping on a silicon. However, suitable CAD tool is absent to support the simulation and verification in high-level. This paper presents a novel modeling and high-level verification methodology based on Petri net (PN) model. By proposed method, a system of DSP algorithm in the form of FSFG is transformed into PN model. Moreover, verification methods which include static and dynamical phases are applied in PN domain. At last, we introduce our software implementation, called HiVED, to show the experimental results.
AB - Formal verification in system-level, which also means architecture verification, is different from functional verification in RTL level. DSP algorithms need high-level transformation to achieve optimal goals before mapping on a silicon. However, suitable CAD tool is absent to support the simulation and verification in high-level. This paper presents a novel modeling and high-level verification methodology based on Petri net (PN) model. By proposed method, a system of DSP algorithm in the form of FSFG is transformed into PN model. Moreover, verification methods which include static and dynamical phases are applied in PN domain. At last, we introduce our software implementation, called HiVED, to show the experimental results.
UR - http://www.scopus.com/inward/record.url?scp=67649135186&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2005.1465925
DO - 10.1109/ISCAS.2005.1465925
M3 - Conference article
AN - SCOPUS:67649135186
SN - 0271-4310
SP - 5674
EP - 5677
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 1465925
T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -