Equations of the electric field, surface charge, and silicon capacitance with respect to the surface potential of single through-silicon via (TSV) are derived by Poisson's equation. Four kinds of charges such as the electrons, holes, and ionized donor/acceptor charges in the p-type silicon substrate are brought into the equations. The numerical results of the surface charge show identical plots to planar MOS capacitor when the TSV radius is larger than 1 μm. After presenting the fundamental C-V characteristics of one TSV capacitor, a simple design for gaining a stable low TSV capacitance value within a wide operating window (|Vow| = 20 V) is proposed. Cu TSVs in this design are then demonstrated in the scheme of the wafer-level Cu/Sn to BCB hybrid bonding. The design gives the rational power consumption and delay, and the guideline for physical IC design is described in this paper. Without the oxide-trapped charge Qot engineering in TSV oxide liner, neither considerations of the VFB shifts nor the doping-type selection in silicon substrate, the design facilitates IC engineers to plan the high-speed TSVs at a specific location and to save the cost from TSV engineering simultaneously.
|頁（從 - 到）||129-135|
|期刊||IEEE Transactions on Device and Materials Reliability|
|出版狀態||Published - 1 一月 2015|