Mixed-VTH (MVT) CMOS circuit design for low power cell libraries

Jiun Yi Lin*, Li Rong Wang, Chia Lin Hu, Shyh-Jye Jou

*此作品的通信作者

    研究成果: Conference contribution同行評審

    3 引文 斯高帕斯(Scopus)

    摘要

    Mixed-Vth (MVT) technique has been proposed to resize the MOS size and then reduce dynamic power in logic gates by applying a low threshold voltage to transistors in some critical paths, while a standard threshold voltage is used in non-critical paths. This paper presents 130nm and 90nm low power cell libraries using MVT technique. The dynamic power consumption of the cells has been reduced around 5% to 30% and with the same timing specifications.

    原文English
    主出版物標題Proceedings - 20th Anniversary IEEE International SOC Conference
    頁面181-184
    頁數4
    DOIs
    出版狀態Published - 2007
    事件20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan
    持續時間: 26 9月 200729 9月 2007

    出版系列

    名字Proceedings - 20th Anniversary IEEE International SOC Conference

    Conference

    Conference20th Anniversary IEEE International SOC Conference
    國家/地區Taiwan
    城市Hsinchu
    期間26/09/0729/09/07

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