TY - JOUR
T1 - Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD supply
AU - Ker, Ming-Dou
AU - Chen, Shih Lun
PY - 2005/12/6
Y1 - 2005/12/6
N2 - This work presents a mixed-voltage I/O buffer realized with 1×V DD devices and single VDD power supply to receive 3×VDD input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13μm 1V CMOS process. This technique can be extended to receive 4×VDD, 5×V DD, and even 6×VDD input signals.
AB - This work presents a mixed-voltage I/O buffer realized with 1×V DD devices and single VDD power supply to receive 3×VDD input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13μm 1V CMOS process. This technique can be extended to receive 4×VDD, 5×V DD, and even 6×VDD input signals.
UR - http://www.scopus.com/inward/record.url?scp=28144440292&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2005.1494100
DO - 10.1109/ISSCC.2005.1494100
M3 - Conference article
AN - SCOPUS:28144443457
SN - 0193-6530
VL - 48
JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
M1 - 28.8
T2 - 2005 IEEE International Solid-State Circuits Conference, ISSCC
Y2 - 6 February 2005 through 10 February 2005
ER -