Mixed signal design of cascadable matched filters

Chau-Chin Su; Hung Chi Lin; Shyh-Jye Jou

doi:10.1109/ISCAS.1997.621573

Mixed signal design of cascadable matched filters

Chau-Chin Su^*, Hung Chi Lin, Shyh-Jye Jou

^*此作品的通信作者

研究成果: Conference article › 同行評審

摘要

This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm² core by 0.8 μm SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.

原文	English
頁（從 - 到）	2108-2111
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	3
DOIs	https://doi.org/10.1109/ISCAS.1997.621573
出版狀態	Published - 1997
事件	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong 持續時間: 9 6月 1997 → 12 6月 1997

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10.1109/ISCAS.1997.621573

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title = "Mixed signal design of cascadable matched filters",

abstract = "This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm2 core by 0.8 μm SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.",

author = "Chau-Chin Su and Lin, {Hung Chi} and Shyh-Jye Jou",

year = "1997",

doi = "10.1109/ISCAS.1997.621573",

language = "English",

volume = "3",

pages = "2108--2111",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) ; Conference date: 09-06-1997 Through 12-06-1997",

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AU - Su, Chau-Chin

AU - Lin, Hung Chi

AU - Jou, Shyh-Jye

PY - 1997

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AB - This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm2 core by 0.8 μm SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.

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U2 - 10.1109/ISCAS.1997.621573

DO - 10.1109/ISCAS.1997.621573

M3 - Conference article

AN - SCOPUS:0030719795

SN - 0271-4310

VL - 3

SP - 2108

EP - 2111

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)

Y2 - 9 June 1997 through 12 June 1997

ER -

Mixed signal design of cascadable matched filters

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