Mix-and-match lithography processes for 0.1 μm MOS transistor device fabrication

Jen Yu Yew*, Lih Juann Chen, Kazumitsu Nakamura, Tien-Sheng Chao, Horng-Chih Lin

*此作品的通信作者

研究成果: Conference article同行評審

1 引文 斯高帕斯(Scopus)

摘要

The mix-and-match method is an effective method to meet the requirements of minimizing the exposure time and the feature size, in which only the critical gate layer is exposured by electron beam lithography system, and the other ones by conventional g-line stepper. The negative type chemically amplified resist SAL601, made by Shipley, has been used for gate fabrication. The optimum conditions for the electron beam lithography including mark dimension, resist process and etching process have been investigated. The accelerating voltage and the beam current were fixed to be 40 kV and 0.25 nA, respectively. The mark of the electron beam lithography has the trench cross shape of 0.5 μm in depth, 20 μm in length and 3 μm in width. The sensitivity of SAL601 resist has been 20 μC/cm2 for 0.1 μm patterning at 40 kV accelerating voltage. The polysilicon gate was etched by electron cyclotron resonance (ECR) with SiO2 thin mask in HBr/O2 gas, for the appropriate anisotropy of etching and for the polysilicon-to-oxide selectivity of HBr/O2 gas plasma. The well defined profile of polysilicon gate with 0.1 μm width has been obtained successfully.

原文English
頁(從 - 到)180-188
頁數9
期刊Proceedings of SPIE - The International Society for Optical Engineering
2723
DOIs
出版狀態Published - 1996
事件Electron-Beam, X-Ray, EUV and Ion-Beam Submicrometer Lithographies for Manufacturing VI - Santa Clara, CA, United States
持續時間: 11 3月 199613 3月 1996

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