Mitigating Power and Process Variation for Analog CIM Design Migration

Computing-in-memory (CIM) is a popular technique for low-power convolution neural network (CNN) applications. In order to keep the accuracy of machine learning model, process variations should be concerned while designing the CIM design. In this paper, we present a low-power design migration flow to migrate the bottleneck analog blocks in an CIM design from planar CMOS to FinFET technology. Starting from the schematic design at 28 nm, the ML-assisted synthesis engine adjusts the device sizes of those analog blocks for 16 nm technology to meet the specifications with power and variation consideration. Because the big difference between planar CMOS and FinFET technology, a transfer learning technology is also proposed to fit the different properties of new process with very few re-training efforts. After sizing stage, a migration-based layout generation is proposed to produce high quality layout in a short time. As shown in the post-layout simulation results, the proposed low-power migration flow is able to generate DRC-clean layout designs in 16 nm technology with up to 34% power reduction and improved design yield. The power and area of the overall CIM design are reduced by 18.4% and 40.9% respectively, which shows the feasibility of our approach to deal with such a large design.