Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse

Chih Cheng Chang, Pin Chun Chen, Teyuh Chou, I. Ting Wang, Boris Hudec, Che Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou*

*此作品的通信作者

研究成果: Article同行評審

58 引文 斯高帕斯(Scopus)

摘要

Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses, because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit data set to 87.8%/94.8% by using 6-/8-b analog synapses, respectively, with extremely high asymmetric nonlinearity.

原文English
頁(從 - 到)116-124
頁數9
期刊IEEE Journal on Emerging and Selected Topics in Circuits and Systems
8
發行號1
DOIs
出版狀態Published - 1 3月 2018

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