Minimizing critical area on gridless wire ordering, sizing and spacing

Yu Wei Lee, Yen Hung Lin, Yih-Lang Li

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)


Design for yield (DFY) problems have received increasing attention. Of particular concern in DFY problems is how to formulate and reduce a critical area for random defects. Arranging interconnects is recognized as an effective means of improving the sensitivity towards random defects. Previous works have demonstrated that random defects significantly influence interconnections and the effectiveness of layer assignment and track routing to enhance routing quality and performance. This work proposes a random defect aware layer assignment and gridless track routing (RAAT) to eliminate the effect of random defects. Gridless track routing comprises wire ordering, wire sizing and spacing in this work. Exposure ratio metric is proposed to assign well each iroute to a specific layer. RAAT utilizes min-cut partitioning, a conventionally adopted method for placement and floorplanning, to place and size interconnections. Slicing tree-based structure improves the efficiency of wire ordering in lowering overlapped length between adjacent partitions. Finally, a second-order corn programming refined by considering an extra random-defect effect determines the position and width of each iroute. Experimental results demonstrate the necessity of the integration of layer assignment and track routing. Results further demonstrate the effectiveness of the gridless track routing methods proposed by RAAT. In addition to finishing each case more rapidly with higher completion rate than previous works do, RAAT reduces up to 20% of the number of failures in the Monte Carlo simulation as compared to previous works.

頁(從 - 到)157-177
期刊Journal of Information Science and Engineering
出版狀態Published - 1 1月 2014


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