Millimeter-Wave CMOS Devices Design With Mobility Enhancement and Parasitic RC Suppression for Super-350 GHz f_T and f_MAX in Multiring nMOSFETs

Multifinger (MF) and multiring (MR) nMOSFETs were designed and fabricated in 40-nm CMOS technology to explore the layout-dependent effects (LDEs) in terms of uniaxial stress, effective mobility (µ_eff), as well as parasitic resistances and capacitances (RC) responsible for the high-frequency performance like unit current gain cut-off frequency, f_T and maximum oscillation frequency, f_MAX. The experimental results prove the advantages of MR nMOSFETs, such as the higher µ_eff and transconductance (g_m), as well as the smaller parasitic source resistance and gate resistance, which can yield record high f_T and f_MAX in 40 nm CMOS technology, up to 360- and 402-GHz, that is 60 and 115-GHz higher than that of MF nMOSFET with the same finger number and width. This superior f_T and f_MAX keep even better than 22 and 14 nm FinFETs. Besides, new methods have been developed to realize accurate extraction of the parasitic RC and µ_eff in sub-40 nm nMOSFETs with various layouts. The precise parameters extraction and modeling of the LDE can facilitate nanoscale device layout optimization, aimed at super-350 GHz f_T and f_MAX for mm-wave CMOS circuit design.