TY - JOUR
T1 - Metrology for analog module testing using analog testability bus
AU - Su, Chau-Chin
AU - Chen, Yue Tsang
AU - Jou, Shyh-Jye
AU - Ting, Yuan Tzu
PY - 1996
Y1 - 1996
N2 - In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic effects in an analog testability bus test environment. For the test response analysis, we derive an extraction methodology to remove the parasitic effects and obtain the intrinsic response of the CUT. The test results show that the algorithm is robust such that the intrinsic responses remain the same regardless of the small variation in the test waveforms. With the concept of intrinsic responses, we are able to use a single library for the testing and diagnosis of multiple instantiation of an analog module.
AB - In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic effects in an analog testability bus test environment. For the test response analysis, we derive an extraction methodology to remove the parasitic effects and obtain the intrinsic response of the CUT. The test results show that the algorithm is robust such that the intrinsic responses remain the same regardless of the small variation in the test waveforms. With the concept of intrinsic responses, we are able to use a single library for the testing and diagnosis of multiple instantiation of an analog module.
UR - http://www.scopus.com/inward/record.url?scp=0030397945&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.1996.569916
DO - 10.1109/ICCAD.1996.569916
M3 - Conference article
AN - SCOPUS:0030397945
SN - 1092-3152
SP - 594
EP - 599
JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
JF - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
M1 - 5465474
T2 - Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design
Y2 - 10 November 1996 through 14 November 1996
ER -