Metrology for analog module testing using analog testability bus

Chau-Chin Su*, Yue Tsang Chen, Shyh-Jye Jou, Yuan Tzu Ting


研究成果: Conference article同行評審

4 引文 斯高帕斯(Scopus)


In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic effects in an analog testability bus test environment. For the test response analysis, we derive an extraction methodology to remove the parasitic effects and obtain the intrinsic response of the CUT. The test results show that the algorithm is robust such that the intrinsic responses remain the same regardless of the small variation in the test waveforms. With the concept of intrinsic responses, we are able to use a single library for the testing and diagnosis of multiple instantiation of an analog module.

頁(從 - 到)594-599
期刊IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
出版狀態Published - 1996
事件Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
持續時間: 10 11月 199614 11月 1996


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