Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology

Hsin Chyh Hsu; Chi Ming Chen; Ming-Dou Ker

doi:10.1109/VTSA.2005.1497064

Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology

Hsin Chyh Hsu^*, Chi Ming Chen, Ming-Dou Ker

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

NMOS with dummy-gate structure is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, the ESD current is discharged far away from the salicided surface channel of NMOS, therefore NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress.

原文	English
主出版物標題	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers
頁面	19-20
頁數	2
DOIs	https://doi.org/10.1109/VTSA.2005.1497064
出版狀態	Published - 31 10月 2005
事件	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH - Hsinchu, Taiwan 持續時間: 25 4月 2005 → 27 4月 2005

出版系列

名字	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Conference

Conference	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH
國家/地區	Taiwan
城市	Hsinchu
期間	25/04/05 → 27/04/05

存取文件

10.1109/VTSA.2005.1497064

其它文件與鏈接

Link to publication in Scopus

引用此

Hsu, H. C., Chen, C. M., & Ker, M.-D. (2005). Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology. 於 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers (頁 19-20). 文章 T13 (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers). https://doi.org/10.1109/VTSA.2005.1497064

Hsu, Hsin Chyh ; Chen, Chi Ming ; Ker, Ming-Dou. / Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology. 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. 頁 19-20 (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers).

@inproceedings{64267ba5ce4d43169a2d206f4e6bebd6,

title = "Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology",

abstract = "NMOS with dummy-gate structure is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, the ESD current is discharged far away from the salicided surface channel of NMOS, therefore NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress.",

author = "Hsu, {Hsin Chyh} and Chen, {Chi Ming} and Ming-Dou Ker",

year = "2005",

month = oct,

day = "31",

doi = "10.1109/VTSA.2005.1497064",

language = "English",

isbn = "078039058X",

series = "2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers",

pages = "19--20",

booktitle = "2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers",

note = "2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH ; Conference date: 25-04-2005 Through 27-04-2005",

}

Hsu, HC, Chen, CM & Ker, M-D 2005, Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology. 於 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers., T13, 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers, 頁 19-20, 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Hsinchu, Taiwan, 25/04/05. https://doi.org/10.1109/VTSA.2005.1497064

Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology. / Hsu, Hsin Chyh; Chen, Chi Ming; Ker, Ming-Dou.
2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. p. 19-20 T13 (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology

AU - Hsu, Hsin Chyh

AU - Chen, Chi Ming

AU - Ker, Ming-Dou

PY - 2005/10/31

Y1 - 2005/10/31

N2 - NMOS with dummy-gate structure is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, the ESD current is discharged far away from the salicided surface channel of NMOS, therefore NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress.

AB - NMOS with dummy-gate structure is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, the ESD current is discharged far away from the salicided surface channel of NMOS, therefore NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress.

UR - http://www.scopus.com/inward/record.url?scp=27144473304&partnerID=8YFLogxK

U2 - 10.1109/VTSA.2005.1497064

DO - 10.1109/VTSA.2005.1497064

M3 - Conference contribution

AN - SCOPUS:27144473304

SN - 078039058X

T3 - 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

SP - 19

EP - 20

BT - 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers

T2 - 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH

Y2 - 25 April 2005 through 27 April 2005

ER -

Hsu HC, Chen CM, Ker MD. Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology. 於 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. p. 19-20. T13. (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers). doi: 10.1109/VTSA.2005.1497064

Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology

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