Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event

Tai Xiang Lai; Ming Dou Ker

doi:10.1109/EDSSC.2005.1635317

Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event

Tai Xiang Lai^*, Ming Dou Ker

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

2 引文斯高帕斯（Scopus）

摘要

Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface. The transmission line pulsing (TLP) system has been the most important method to observe electric characteristics of the device under human-body-model (HBM) ESD stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of CDE on the Ethernet integrated circuits, and the results are compared with conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-μm CMOS technology is much worse than its HBM electrostatic discharge robustness.

原文	English
主出版物標題	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	499-502
頁數	4
ISBN（列印）	0780393392, 9780780393394
DOIs	https://doi.org/10.1109/EDSSC.2005.1635317
出版狀態	Published - 2005
事件	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC - Howloon, Hong Kong 持續時間: 19 12月 2005 → 21 12月 2005

出版系列

名字	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

Conference

Conference	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
國家/地區	Hong Kong
城市	Howloon
期間	19/12/05 → 21/12/05

存取文件

10.1109/EDSSC.2005.1635317

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Link to publication in Scopus

引用此

Lai, T. X., & Ker, M. D. (2005). Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event. 於 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC (頁 499-502). 文章 1635317 (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2005.1635317

@inproceedings{be2e473bc6c34c05b1faf1c4907699e1,

title = "Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event",

abstract = "Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface. The transmission line pulsing (TLP) system has been the most important method to observe electric characteristics of the device under human-body-model (HBM) ESD stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of CDE on the Ethernet integrated circuits, and the results are compared with conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-μm CMOS technology is much worse than its HBM electrostatic discharge robustness.",

author = "Lai, {Tai Xiang} and Ker, {Ming Dou}",

year = "2005",

doi = "10.1109/EDSSC.2005.1635317",

language = "English",

isbn = "0780393392",

series = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "499--502",

booktitle = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC",

address = "United States",

note = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC ; Conference date: 19-12-2005 Through 21-12-2005",

}

Lai, TX & Ker, MD 2005, Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event. 於 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC., 1635317, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, Institute of Electrical and Electronics Engineers Inc., 頁 499-502, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, Howloon, Hong Kong, 19/12/05. https://doi.org/10.1109/EDSSC.2005.1635317

Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event. / Lai, Tai Xiang; Ker, Ming Dou.
2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. Institute of Electrical and Electronics Engineers Inc., 2005. p. 499-502 1635317 (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event

AU - Lai, Tai Xiang

AU - Ker, Ming Dou

PY - 2005

Y1 - 2005

N2 - Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface. The transmission line pulsing (TLP) system has been the most important method to observe electric characteristics of the device under human-body-model (HBM) ESD stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of CDE on the Ethernet integrated circuits, and the results are compared with conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-μm CMOS technology is much worse than its HBM electrostatic discharge robustness.

AB - Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface. The transmission line pulsing (TLP) system has been the most important method to observe electric characteristics of the device under human-body-model (HBM) ESD stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of CDE on the Ethernet integrated circuits, and the results are compared with conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-μm CMOS technology is much worse than its HBM electrostatic discharge robustness.

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U2 - 10.1109/EDSSC.2005.1635317

DO - 10.1109/EDSSC.2005.1635317

M3 - Conference contribution

AN - SCOPUS:43549093255

SN - 0780393392

SN - 9780780393394

T3 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

SP - 499

EP - 502

BT - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

Y2 - 19 December 2005 through 21 December 2005

ER -

Lai TX, Ker MD. Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event. 於 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. Institute of Electrical and Electronics Engineers Inc. 2005. p. 499-502. 1635317. (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC). doi: 10.1109/EDSSC.2005.1635317

Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event

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Conference

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