Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

Jen Chou Tseng*, Yu Lin Chen, Chung Ti Hsu, Fu Yi Tsai, Po An Chen, Ming-Dou Ker

*此作品的通信作者

    研究成果: Conference contribution同行評審

    3 引文 斯高帕斯(Scopus)

    摘要

    An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated circuits. The latchup test resulted in damage to the output NMOSFET due to snapback and also resulted in a latchup in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.

    原文English
    主出版物標題46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS
    頁面625-626
    頁數2
    DOIs
    出版狀態Published - 17 9月 2008
    事件46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS - Phoenix, AZ, United States
    持續時間: 27 4月 20081 5月 2008

    出版系列

    名字IEEE International Reliability Physics Symposium Proceedings
    ISSN(列印)1541-7026

    Conference

    Conference46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS
    國家/地區United States
    城市Phoenix, AZ
    期間27/04/081/05/08

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