Mechanism behind Long Line-Type MCUs in Thin-BOX SOI SRAMs: Resistance-Based Modeling and Countermeasure

Chin Han Chung, Daisuke Kobayashi, Kazuyuki Hirose

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

Silicon-on-insulator (SOI) technology has been considered capable of developing devices with high tolerance against soft error. With a thin buried oxide (BOX) layer, reduction in power consumption can be achieved by applying a back bias from under the BOX. Such power reduction is one of its many advantages and is appealing to space applications. Recently, it was found during a heavy ion experiment that a static random access memory (SRAM) fabricated with a thin-BOX SOI technology exhibits a 100-fold soft error sensitivity when it receives a back-bias. This is due to long line-type formation of multiple cell upsets (MCUs). To understand the mechanism of this phenomenon and the effects of device parameters on it, an analytical model is developed and studied with numerical simulation. On the basis of the model, a countermeasure is also discussed. It is found that the deep n-well doping concentration or resistance plays an important role in the phenomenon and its countermeasure.

原文English
主出版物標題2017 17th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2017
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538612613
DOIs
出版狀態Published - 2 7月 2017
事件17th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2017 - Geneva, Switzerland
持續時間: 2 10月 20176 10月 2017

出版系列

名字2017 17th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2017

Conference

Conference17th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2017
國家/地區Switzerland
城市Geneva
期間2/10/176/10/17

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