TY - GEN
T1 - Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration
AU - Chen, Wen Yi
AU - Ker, Ming-Dou
AU - Huang, Yeh Jen
AU - Jou, Yeh Ning
AU - Lin, Geeng Lih
PY - 2008/12/1
Y1 - 2008/12/1
N2 - In high voltage (HV) ICs, the latch-up immunity of HV devices is often referred to the TLP-measured holding voltage because the huge power generated from DC curve tracer can easily damage HV device during measurement. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-μm 18-V bipolar CMOS DMOS (BCD) process to investigate the validity of TLP-measured snapback holding voltage to the device immunity against latch-up. Experimental results from curve tracer measurement and transient latch-up test show that 100-ns TLP underestimates the latch-up susceptibility of the 18-V LDMOS. By using the long-pulse TLP measurement, snapback holding voltage of the HV device has been found to degrade over time due to the self-heating effect. As a result, since the latch-up event is a reliability test with the time duration longer than millisecond, TLP measurement is not suitable for applying to investigate the snapback holding voltage of HV devices for latch-up.
AB - In high voltage (HV) ICs, the latch-up immunity of HV devices is often referred to the TLP-measured holding voltage because the huge power generated from DC curve tracer can easily damage HV device during measurement. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-μm 18-V bipolar CMOS DMOS (BCD) process to investigate the validity of TLP-measured snapback holding voltage to the device immunity against latch-up. Experimental results from curve tracer measurement and transient latch-up test show that 100-ns TLP underestimates the latch-up susceptibility of the 18-V LDMOS. By using the long-pulse TLP measurement, snapback holding voltage of the HV device has been found to degrade over time due to the self-heating effect. As a result, since the latch-up event is a reliability test with the time duration longer than millisecond, TLP measurement is not suitable for applying to investigate the snapback holding voltage of HV devices for latch-up.
UR - http://www.scopus.com/inward/record.url?scp=62949233346&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2008.4745960
DO - 10.1109/APCCAS.2008.4745960
M3 - Conference contribution
AN - SCOPUS:62949233346
SN - 9781424423422
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 61
EP - 64
BT - Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
T2 - APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Y2 - 30 November 2008 through 3 December 2008
ER -