Mask versus Schematic - An enhanced design-verification flow for first silicon success

Tseng Chin Luo*, Eric Leong, Chia-Tso Chao, Philip A. Fisher, Wen Hsiang Chang

*此作品的通信作者

    研究成果: Conference contribution同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    Layout versus Schematic (LVS) is a commonly used technique employed at the design stage to insure the correctness of physical layout. However, as process technologies continually advance, increasingly complex boolean operations are required to produce the desired on-mask patterns, which are frequently optimized to enhance transistor performance and process margin. Design layout which has been verified by LVS may undergo substantial layout changes when subjected to the mask generation booleans, with potential implications for performance and margin estimation, particularly given the aggressive use of stressors in modern CMOS technologies. Errors in mask generation booleans, which are very difficult to detect by present primitive inspection methods, can easily result in functional failure although the initial LVS predicted success. Therefore, LVS performed at the design stage is no longer an iron-clad guarantee of chip functionality in advanced process technologies. In this paper, we introduce Mask-versus-Schematic (MVS) verification, a novel design verification flow which directly compares the schematic netlist with a netlist extracted after application of all mask generation booleans, in order to insure the correctness of the final mask data just before tapeout. Furthermore, the introduced methodology can be performed using currently available physical verification EDA tools. The experimental results presented here, using examples from some of the industry's most advanced process technology nodes, demonstrate the effectiveness and efficiency of this methodology in detecting errors resulting from mask generation boolean operations.

    原文English
    主出版物標題Proceedings - International Test Conference 2010, ITC 2010
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISBN(列印)9781424472055
    DOIs
    出版狀態Published - 2010
    事件41st International Test Conference, ITC 2010 - Austin, TX, United States
    持續時間: 31 10月 20105 11月 2010

    出版系列

    名字Proceedings - International Test Conference
    ISSN(列印)1089-3539

    Conference

    Conference41st International Test Conference, ITC 2010
    國家/地區United States
    城市Austin, TX
    期間31/10/105/11/10

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