MapReduce-based pattern classification for design space analysis

Yan Shiun Wu; Hong Yan Su; Yi Hsiang Chang; Rasit Onur Topaloglu; Yih-Lang Li

doi:10.1109/VLSI-DAT.2018.8373275

MapReduce-based pattern classification for design space analysis

Yan Shiun Wu, Hong Yan Su, Yi Hsiang Chang, Rasit Onur Topaloglu, Yih-Lang Li

資訊科學與工程研究所

研究成果: Conference contribution › 同行評審

3 引文斯高帕斯（Scopus）

摘要

With the ongoing reduction of feature size, design for manufacturability is a critical concern in advanced technology nodes. Pattern classification is a promising and widely employed approach for design space analysis, design rule generation, and yield optimization. In this paper, we propose a hybrid algorithm that account for two variations for classification metrics: feature edge displacement and total feature area difference. A MapRe-duce-based framework is proposed to reduce the complexity of the pattern classification problem such that orders of magnitude of performance improvement can be realized. Our experimental results indicate that regarding accuracy and runtime, this work out-performs the winner of the CAD Contest at ICCAD 2016 in terms of contest scoring measure.

原文	English
主出版物標題	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	1-4
頁數	4
ISBN（電子）	9781538642603
DOIs	https://doi.org/10.1109/VLSI-DAT.2018.8373275
出版狀態	Published - 5 6月 2018
事件	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, 台灣持續時間: 16 4月 2018 → 19 4月 2018

出版系列

名字	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Conference

Conference	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
國家/地區	台灣
城市	Hsinchu
期間	16/04/18 → 19/04/18

存取文件

10.1109/VLSI-DAT.2018.8373275

其它文件與鏈接

Link to publication in Scopus

引用此

Wu, Y. S., Su, H. Y., Chang, Y. H., Topaloglu, R. O., & Li, Y.-L. (2018). MapReduce-based pattern classification for design space analysis. 於 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 (頁 1-4). (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2018.8373275

@inproceedings{00a2262bd3bb429d9780d4fea11db5ca,

title = "MapReduce-based pattern classification for design space analysis",

abstract = "With the ongoing reduction of feature size, design for manufacturability is a critical concern in advanced technology nodes. Pattern classification is a promising and widely employed approach for design space analysis, design rule generation, and yield optimization. In this paper, we propose a hybrid algorithm that account for two variations for classification metrics: feature edge displacement and total feature area difference. A MapRe-duce-based framework is proposed to reduce the complexity of the pattern classification problem such that orders of magnitude of performance improvement can be realized. Our experimental results indicate that regarding accuracy and runtime, this work out-performs the winner of the CAD Contest at ICCAD 2016 in terms of contest scoring measure.",

keywords = "MapReduce, Pr{\"u}fer encoding, design for manufacturability, pattern classification",

author = "Wu, {Yan Shiun} and Su, {Hong Yan} and Chang, {Yi Hsiang} and Topaloglu, {Rasit Onur} and Yih-Lang Li",

year = "2018",

month = jun,

day = "5",

doi = "10.1109/VLSI-DAT.2018.8373275",

language = "English",

series = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--4",

booktitle = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",

address = "美國",

note = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 ; Conference date: 16-04-2018 Through 19-04-2018",

}

Wu, YS, Su, HY, Chang, YH, Topaloglu, RO & Li, Y-L 2018, MapReduce-based pattern classification for design space analysis. 於 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Institute of Electrical and Electronics Engineers Inc., 頁 1-4, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Hsinchu, 台灣, 16/04/18. https://doi.org/10.1109/VLSI-DAT.2018.8373275

MapReduce-based pattern classification for design space analysis. / Wu, Yan Shiun; Su, Hong Yan; Chang, Yi Hsiang 等.
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018).

研究成果: Conference contribution › 同行評審

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T1 - MapReduce-based pattern classification for design space analysis

AU - Wu, Yan Shiun

AU - Su, Hong Yan

AU - Chang, Yi Hsiang

AU - Topaloglu, Rasit Onur

AU - Li, Yih-Lang

PY - 2018/6/5

Y1 - 2018/6/5

N2 - With the ongoing reduction of feature size, design for manufacturability is a critical concern in advanced technology nodes. Pattern classification is a promising and widely employed approach for design space analysis, design rule generation, and yield optimization. In this paper, we propose a hybrid algorithm that account for two variations for classification metrics: feature edge displacement and total feature area difference. A MapRe-duce-based framework is proposed to reduce the complexity of the pattern classification problem such that orders of magnitude of performance improvement can be realized. Our experimental results indicate that regarding accuracy and runtime, this work out-performs the winner of the CAD Contest at ICCAD 2016 in terms of contest scoring measure.

AB - With the ongoing reduction of feature size, design for manufacturability is a critical concern in advanced technology nodes. Pattern classification is a promising and widely employed approach for design space analysis, design rule generation, and yield optimization. In this paper, we propose a hybrid algorithm that account for two variations for classification metrics: feature edge displacement and total feature area difference. A MapRe-duce-based framework is proposed to reduce the complexity of the pattern classification problem such that orders of magnitude of performance improvement can be realized. Our experimental results indicate that regarding accuracy and runtime, this work out-performs the winner of the CAD Contest at ICCAD 2016 in terms of contest scoring measure.

KW - MapReduce

KW - Prüfer encoding

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KW - pattern classification

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M3 - Conference contribution

AN - SCOPUS:85049317704

T3 - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

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BT - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

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Wu YS, Su HY, Chang YH, Topaloglu RO, Li YL. MapReduce-based pattern classification for design space analysis. 於 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4. (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). doi: 10.1109/VLSI-DAT.2018.8373275

MapReduce-based pattern classification for design space analysis

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Conference

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