Low-voltage low-power IF-baseband digital down converter

Shyh-Jye Jou*, Tsan I. Hsu, C. K. Wang

*此作品的通信作者

研究成果: Paper同行評審

摘要

A low-voltage low-power all digital down converter (ADDC) is presented for implementing the IF front end signal processing. The ADDC chip accepts a 5-bits digitized intermediate-frequency (IF) input signal and generates a pair of 10-bits filtered in-phase and quadrature baseband signals. Low power consumption is main design consideration in this ADDC chip. Thus, many low power design technologies that include algorithm, architecture and circuit level are used to keep the power dissipation minimum. The ADDC has a symbol rate of 1.2288 MHz (clock rate 19.6608 MHz) and 1 mW average power dissipation when operated in 2 V power supply. The chip was fabricated in a 0.8 μm single poly double metal CMOS process. The core area is 2.45 mm2 and is composed of 12,100 transistors.

原文English
頁面270-274
頁數5
DOIs
出版狀態Published - 1997
事件Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China
持續時間: 3 6月 19975 6月 1997

Conference

ConferenceProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
城市Taipei, China
期間3/06/975/06/97

指紋

深入研究「Low-voltage low-power IF-baseband digital down converter」主題。共同形成了獨特的指紋。

引用此