Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

Chun Chiang; Ping Chen Chang; Mei Ling Chao; Tien Hao Tang; Kuan Cheng Su; Ming-Dou Ker

doi:10.1109/IPFA.2017.8060226

Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

Chun Chiang, Ping Chen Chang, Mei Ling Chao, Tien Hao Tang, Kuan Cheng Su, Ming-Dou Ker

電子研究所

研究成果: Conference contribution › 同行評審

2 引文斯高帕斯（Scopus）

摘要

According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (V_BD) and low holding voltage (V_h) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM<8kV) and good turn-on efficiency (V_t1=8.1V) without suffering from low V_BD and latch-up issues.

原文	English
主出版物標題	24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	1-3
頁數	3
ISBN（電子）	9781538617793
DOIs	https://doi.org/10.1109/IPFA.2017.8060226
出版狀態	Published - 5 10月 2017
事件	24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 - Chengdu, China 持續時間: 4 7月 2017 → 7 7月 2017

出版系列

名字	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
卷	2017-July

Conference

Conference	24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
國家/地區	China
城市	Chengdu
期間	4/07/17 → 7/07/17

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10.1109/IPFA.2017.8060226

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Link to publication in Scopus

引用此

Chiang, C., Chang, P. C., Chao, M. L., Tang, T. H., Su, K. C., & Ker, M-D. (2017). Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering. 於 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 (頁 1-3). (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; 卷 2017-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA.2017.8060226

Chiang, Chun ; Chang, Ping Chen ; Chao, Mei Ling 等. / Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering. 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 頁 1-3 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{9c68d1b849644cc6a0ae001cc9ae2c79,

title = "Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering",

abstract = "According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (VBD) and low holding voltage (Vh) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM<8kV) and good turn-on efficiency (Vt1=8.1V) without suffering from low VBD and latch-up issues.",

author = "Chun Chiang and Chang, {Ping Chen} and Chao, {Mei Ling} and Tang, {Tien Hao} and Su, {Kuan Cheng} and Ming-Dou Ker",

year = "2017",

month = oct,

day = "5",

doi = "10.1109/IPFA.2017.8060226",

language = "English",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--3",

booktitle = "24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017",

address = "United States",

note = "24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 ; Conference date: 04-07-2017 Through 07-07-2017",

}

Chiang, C, Chang, PC, Chao, ML, Tang, TH, Su, KC & Ker, M-D 2017, Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering. 於 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017. Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 卷 2017-July, Institute of Electrical and Electronics Engineers Inc., 頁 1-3, 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017, Chengdu, China, 4/07/17. https://doi.org/10.1109/IPFA.2017.8060226

Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering. / Chiang, Chun; Chang, Ping Chen; Chao, Mei Ling 等.
24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-3 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; 卷 2017-July).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

AU - Chiang, Chun

AU - Chang, Ping Chen

AU - Chao, Mei Ling

AU - Tang, Tien Hao

AU - Su, Kuan Cheng

AU - Ker, Ming-Dou

PY - 2017/10/5

Y1 - 2017/10/5

N2 - According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (VBD) and low holding voltage (Vh) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM<8kV) and good turn-on efficiency (Vt1=8.1V) without suffering from low VBD and latch-up issues.

AB - According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (VBD) and low holding voltage (Vh) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM<8kV) and good turn-on efficiency (Vt1=8.1V) without suffering from low VBD and latch-up issues.

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U2 - 10.1109/IPFA.2017.8060226

DO - 10.1109/IPFA.2017.8060226

M3 - Conference contribution

AN - SCOPUS:85045065262

T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

SP - 1

EP - 3

BT - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017

Y2 - 4 July 2017 through 7 July 2017

ER -

Chiang C, Chang PC, Chao ML, Tang TH, Su KC, Ker M-D. Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering. 於 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1-3. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2017.8060226

Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

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