Low threshold voltage CMOSFETs with NiSi fully silicided gate and modified schottky barrier source/drain junction

Chia Pin Lin*, Bing-Yue Tsui, Chih Ming Hsieh, Chih Feng Huang

*此作品的通信作者

    研究成果: Conference contribution同行評審

    摘要

    Low threshold voltage CMOSFETs with NiSi fully silicided gate and Modified Schottky barrier source/drain junction were fabricated. Symmetric threshold voltage was obtained by implant-to-silicide technique. Lateral growth rate and thermal stability of NiSi on SiO2 were investigated. Single suicide and low temperature process make the proposed process very promising in sub-45nm technology nodes.

    原文English
    主出版物標題2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Proceedings of Technical Papers
    DOIs
    出版狀態Published - 2007
    事件2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Hsinchu, Taiwan
    持續時間: 23 4月 200725 4月 2007

    出版系列

    名字International Symposium on VLSI Technology, Systems, and Applications, Proceedings

    Conference

    Conference2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
    國家/地區Taiwan
    城市Hsinchu
    期間23/04/0725/04/07

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