@inproceedings{878afe871cfe4760a1d0a7048699e258,
title = "Low temperature polycrystalline Si nanowire devices with gate-all-around Al 2 O 3 /TiN structure using an implant-free technique",
abstract = " In this work, for the first time, we propose and demonstrate an implant-free gate-all-around (GAA) low-temperature poly-Si (LTPS) nanowire (NW) device with Al 2 O 3 dielectric and TiN gate. Since the channel and source/drain (S/D) regions are sharing one in-situ phosphorous-doped poly-Si material, the process cost could be efficiently reduced. Such novel scheme appears to be promising for both system-on-panel (SOP) and three dimensional IC applications. High on-off current ratio and on-state performance are demonstrated for the new device.",
keywords = "gate-all-around (GAA), in-situ doped channel, low temperature poly-Si (LTPS), Si nanowire (Si NW)",
author = "Tsai, {T. I.} and Tien-Sheng Chao and Su, {C. J.} and Lin, {H. C.} and Huang, {T. Y.} and Horng-Chih Lin and Wei, {Y. J.}",
year = "2011",
month = sep,
day = "26",
doi = "10.1109/INEC.2011.5991733",
language = "English",
isbn = "9781457703799",
series = "Proceedings - International NanoElectronics Conference, INEC",
booktitle = "4th IEEE International NanoElectronics Conference, INEC 2011",
note = "null ; Conference date: 21-06-2011 Through 24-06-2011",
}