Low temperature polycrystalline Si nanowire devices with gate-all-around Al 2 O 3 /TiN structure using an implant-free technique

T. I. Tsai*, Tien-Sheng Chao, C. J. Su, H. C. Lin, T. Y. Huang, Horng-Chih Lin, Y. J. Wei

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

In this work, for the first time, we propose and demonstrate an implant-free gate-all-around (GAA) low-temperature poly-Si (LTPS) nanowire (NW) device with Al2O3 dielectric and TiN gate. Since the channel and source/drain (S/D) regions are sharing one in-situ phosphorous-doped poly-Si material, the process cost could be efficiently reduced. Such novel scheme appears to be promising for both system-on-panel (SOP) and three dimensional IC applications. High on-off current ratio and on-state performance are demonstrated for the new device.

原文English
主出版物標題4th IEEE International NanoElectronics Conference, INEC 2011
DOIs
出版狀態Published - 2011
事件4th IEEE International Nanoelectronics Conference, INEC 2011 - Tao-Yuan, Taiwan
持續時間: 21 6月 201124 6月 2011

出版系列

名字Proceedings - International NanoElectronics Conference, INEC
ISSN(列印)2159-3523

Conference

Conference4th IEEE International Nanoelectronics Conference, INEC 2011
國家/地區Taiwan
城市Tao-Yuan
期間21/06/1124/06/11

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