Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration

Yu San Chien; Yan Pin Huang; Ruoh Ning Tzeng; Ming Shaw Shy; Teu Hua Lin; Kou Hua Chen; Ching Te Chuang; Wei Hwang; Jin-Chern Chiou; Chi Tsung Chiu; Ho Ming Tong; Kuan-Neng Chen

doi:10.1109/ECTC.2013.6575718

Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration

Yu San Chien^*, Yan Pin Huang, Ruoh Ning Tzeng, Ming Shaw Shy, Teu Hua Lin, Kou Hua Chen, Ching Te Chuang, Wei Hwang, Jin-Chern Chiou, Chi Tsung Chiu, Ho Ming Tong, Kuan-Neng Chen

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

10 引文斯高帕斯（Scopus）

摘要

Two bonded structures, Cu/In bonding and Cu-Cu bonding with Ti passivation, were investigated for the application of 3D interconnects. For Cu/In bonding, the bonds were achieved at 170°C due to the isothermal solidification. The intermetallic compounds formed in the joint was Cu₂In phase. For another case, Cu-Cu bonding with Ti passivation was successfully achieved at 180°C Application of Ti passivation can protect inner Cu from oxidation; therefore, the required bonding temperature can be decreased. Compared to direct Cu-Cu bonding, Cu/In bonding and Cu-Cu bonding with Ti passivation can be performed at low temperature, which can meet low thermal budget requirement for most devices. Besides, with the good electrical performance and reliability, these two bonded interconnects can be applied for 3D IC interconnects.

原文	English
主出版物標題	2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
發行者	IEEE
頁面	1146-1152
頁數	7
ISBN（列印）	9781479902330
DOIs	https://doi.org/10.1109/ECTC.2013.6575718
出版狀態	Published - 9 9月 2013
事件	2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 - Las Vegas, NV, United States 持續時間: 28 5月 2013 → 31 5月 2013

出版系列

名字	Proceedings - Electronic Components and Technology Conference
ISSN（列印）	0569-5503

Conference

Conference	2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
國家/地區	United States
城市	Las Vegas, NV
期間	28/05/13 → 31/05/13

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10.1109/ECTC.2013.6575718

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Link to publication in Scopus

引用此

Chien, Y. S., Huang, Y. P., Tzeng, R. N., Shy, M. S., Lin, T. H., Chen, K. H., Chuang, C. T., Hwang, W., Chiou, J-C., Chiu, C. T., Tong, H. M., & Chen, K-N. (2013). Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration. 於 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 (頁 1146-1152). [6575718] (Proceedings - Electronic Components and Technology Conference). IEEE. https://doi.org/10.1109/ECTC.2013.6575718

@inproceedings{7f68e487c8a64236b27ff6bb69d4830d,

title = "Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration",

abstract = "Two bonded structures, Cu/In bonding and Cu-Cu bonding with Ti passivation, were investigated for the application of 3D interconnects. For Cu/In bonding, the bonds were achieved at 170°C due to the isothermal solidification. The intermetallic compounds formed in the joint was Cu2In phase. For another case, Cu-Cu bonding with Ti passivation was successfully achieved at 180°C Application of Ti passivation can protect inner Cu from oxidation; therefore, the required bonding temperature can be decreased. Compared to direct Cu-Cu bonding, Cu/In bonding and Cu-Cu bonding with Ti passivation can be performed at low temperature, which can meet low thermal budget requirement for most devices. Besides, with the good electrical performance and reliability, these two bonded interconnects can be applied for 3D IC interconnects.",

author = "Chien, {Yu San} and Huang, {Yan Pin} and Tzeng, {Ruoh Ning} and Shy, {Ming Shaw} and Lin, {Teu Hua} and Chen, {Kou Hua} and Chuang, {Ching Te} and Wei Hwang and Jin-Chern Chiou and Chiu, {Chi Tsung} and Tong, {Ho Ming} and Kuan-Neng Chen",

year = "2013",

month = sep,

day = "9",

doi = "10.1109/ECTC.2013.6575718",

language = "English",

isbn = "9781479902330",

series = "Proceedings - Electronic Components and Technology Conference",

publisher = "IEEE",

pages = "1146--1152",

booktitle = "2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013",

note = "null ; Conference date: 28-05-2013 Through 31-05-2013",

}

Chien, YS, Huang, YP, Tzeng, RN, Shy, MS, Lin, TH, Chen, KH, Chuang, CT, Hwang, W, Chiou, J-C, Chiu, CT, Tong, HM & Chen, K-N 2013, Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration. 於 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013., 6575718, Proceedings - Electronic Components and Technology Conference, IEEE, 頁 1146-1152, 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013, Las Vegas, NV, United States, 28/05/13. https://doi.org/10.1109/ECTC.2013.6575718

Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration. / Chien, Yu San; Huang, Yan Pin; Tzeng, Ruoh Ning 等.

2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013. IEEE, 2013. p. 1146-1152 6575718 (Proceedings - Electronic Components and Technology Conference).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration

AU - Chien, Yu San

AU - Huang, Yan Pin

AU - Tzeng, Ruoh Ning

AU - Shy, Ming Shaw

AU - Lin, Teu Hua

AU - Chen, Kou Hua

AU - Chuang, Ching Te

AU - Hwang, Wei

AU - Chiou, Jin-Chern

AU - Chiu, Chi Tsung

AU - Tong, Ho Ming

AU - Chen, Kuan-Neng

PY - 2013/9/9

Y1 - 2013/9/9

N2 - Two bonded structures, Cu/In bonding and Cu-Cu bonding with Ti passivation, were investigated for the application of 3D interconnects. For Cu/In bonding, the bonds were achieved at 170°C due to the isothermal solidification. The intermetallic compounds formed in the joint was Cu2In phase. For another case, Cu-Cu bonding with Ti passivation was successfully achieved at 180°C Application of Ti passivation can protect inner Cu from oxidation; therefore, the required bonding temperature can be decreased. Compared to direct Cu-Cu bonding, Cu/In bonding and Cu-Cu bonding with Ti passivation can be performed at low temperature, which can meet low thermal budget requirement for most devices. Besides, with the good electrical performance and reliability, these two bonded interconnects can be applied for 3D IC interconnects.

AB - Two bonded structures, Cu/In bonding and Cu-Cu bonding with Ti passivation, were investigated for the application of 3D interconnects. For Cu/In bonding, the bonds were achieved at 170°C due to the isothermal solidification. The intermetallic compounds formed in the joint was Cu2In phase. For another case, Cu-Cu bonding with Ti passivation was successfully achieved at 180°C Application of Ti passivation can protect inner Cu from oxidation; therefore, the required bonding temperature can be decreased. Compared to direct Cu-Cu bonding, Cu/In bonding and Cu-Cu bonding with Ti passivation can be performed at low temperature, which can meet low thermal budget requirement for most devices. Besides, with the good electrical performance and reliability, these two bonded interconnects can be applied for 3D IC interconnects.

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U2 - 10.1109/ECTC.2013.6575718

DO - 10.1109/ECTC.2013.6575718

M3 - Conference contribution

AN - SCOPUS:84883430271

SN - 9781479902330

T3 - Proceedings - Electronic Components and Technology Conference

SP - 1146

EP - 1152

BT - 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013

PB - IEEE

Y2 - 28 May 2013 through 31 May 2013

ER -

Chien YS, Huang YP, Tzeng RN, Shy MS, Lin TH, Chen KH 等. Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration. 於 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013. IEEE. 2013. p. 1146-1152. 6575718. (Proceedings - Electronic Components and Technology Conference). doi: 10.1109/ECTC.2013.6575718

Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration

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Conference

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