Low temperature 12 ns DRAM

W. H. Henkels*, N. C.C. Lu, Wei Hwang, T. V. Rajeevakumar, R. L. Franch, K. A. Jenkins, T. J. Bucelot, D. F. Heidel, M. J. Immediato

*此作品的通信作者

研究成果: Paper同行評審

3 引文 斯高帕斯(Scopus)

摘要

Results are presented of measurements on cryogenic operation of a high-speed 512-kb CMOS dynamic RAM (DRAM). Comprehensive investigations focused on circuit concerns particularly relevant to high speed. The measured access time was 12 ns, and the results show that noise, power, and soft error rate do not preclude very-high-speed DRAM operation at cryogenic temperatures. Compared to room-temperature operation the observed improvement in access time was about 1.7× for VDD = 5 V. Compared to 85°C operation the improvement was 2.2×.

原文English
頁面32-35
頁數4
出版狀態Published - 1 12月 1989
事件International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan
持續時間: 17 5月 198919 5月 1989

Conference

ConferenceInternational Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers
城市Taipei, Taiwan
期間17/05/8919/05/89

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