Results are presented of measurements on cryogenic operation of a high-speed 512-kb CMOS dynamic RAM (DRAM). Comprehensive investigations focused on circuit concerns particularly relevant to high speed. The measured access time was 12 ns, and the results show that noise, power, and soft error rate do not preclude very-high-speed DRAM operation at cryogenic temperatures. Compared to room-temperature operation the observed improvement in access time was about 1.7× for VDD = 5 V. Compared to 85°C operation the improvement was 2.2×.
|出版狀態||Published - 1 12月 1989|
|事件||International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan|
持續時間: 17 5月 1989 → 19 5月 1989
|Conference||International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers|
|期間||17/05/89 → 19/05/89|