Low switching noise and load-adaptive output buffer design techniques

Shyh-Jye Jou*, Shu Hua Kuo, Jui Ta Chiu, Tin Hao Lin

*此作品的通信作者

研究成果: Article同行評審

32 引文 斯高帕斯(Scopus)

摘要

Switching noise due to di/dt is becoming severe as technology scales, resulting in a great need for noise-suppression techniques. Several techniques to reduce the switching noise caused by output buffers in CMOS chips are described. An ac/dc output buffer design technique is proposed that includes an innovative feedback mechanism to reduce switching noise and output signal ringing while at the same time maintains timing and dc current requirement. Also, a technique of adaptively separated simultaneous switching noise is proposed that can increase the number of simultaneously switching outputs per VDD and GND pair. Measurement results show that the ac/dc buffer can reduce the output ringing by 2.5× and VDD/GND line bounce by 1.7× and the ASN can double the number of simultaneous switching outputs under the same conditions as compared to the weighted and distributed buffer.

原文English
頁(從 - 到)1239-1249
頁數11
期刊IEEE Journal of Solid-State Circuits
36
發行號8
DOIs
出版狀態Published - 1 8月 2001

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