Low-spur technique for integer-N phase-locked loop

Te Wen Liao*, Jun Ren Su, Chung-Chih Hung

*此作品的通信作者

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output of the PLL. A new random clock generator is presented to perform a random selection of phase frequency detector (PFD) control for charge pump at locked state. The proposed frequency synthesizer was fabricated in TSMC 0.18-μm CMOS process. The PLL has achieved the phase noise of -105 dBc/Hz at 1MHz offset frequency and reference spurs below -72dBc.

原文English
主出版物標題2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
頁面546-549
頁數4
DOIs
出版狀態Published - 2012
事件2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 - Boise, ID, United States
持續時間: 5 8月 20128 8月 2012

出版系列

名字Midwest Symposium on Circuits and Systems
ISSN(列印)1548-3746

Conference

Conference2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
國家/地區United States
城市Boise, ID
期間5/08/128/08/12

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