@inproceedings{78602700b1c7434f80f21dd8ce37da35,
title = "Low-spur technique for integer-N phase-locked loop",
abstract = "In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output of the PLL. A new random clock generator is presented to perform a random selection of phase frequency detector (PFD) control for charge pump at locked state. The proposed frequency synthesizer was fabricated in TSMC 0.18-μm CMOS process. The PLL has achieved the phase noise of -105 dBc/Hz at 1MHz offset frequency and reference spurs below -72dBc.",
keywords = "PLL, Synthesizer, low spur",
author = "Liao, {Te Wen} and Su, {Jun Ren} and Chung-Chih Hung",
year = "2012",
doi = "10.1109/MWSCAS.2012.6292078",
language = "English",
isbn = "9781467325264",
series = "Midwest Symposium on Circuits and Systems",
pages = "546--549",
booktitle = "2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012",
note = "2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 ; Conference date: 05-08-2012 Through 08-08-2012",
}