## 摘要

This article presents a high throughput and low routing complexity multiframe pipelined low-density parity check (LDPC) decoder design based on a novel pseudo marginalized min-sum (PMMS) message passing approach. The proposed PMMS approach reduces the required number of interconnections in the routing network allowing the design to be implemented with reduced hardware complexity, low power consumption and high throughput capability while supporting multiple coding rates with short and long codewords as defined in many application standards. Implementation results for IEEE802.11ad/ay standards show that the proposed design satisfies a target bit error rate (BER) requirement of <inline-formula> <tex-math notation="LaTeX">$3$</tex-math> </inline-formula> <inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> <inline-formula> <tex-math notation="LaTeX">$10^{-7}$</tex-math> </inline-formula> with 64 quadrature amp mod (QAM) targeting high throughput applications. Furthermore, the proposed design is able to achieve a throughput of 62 and 101.8 Gb/s with two pipelining stages under 28-nm CMOS and 16-nm FinFET CMOS process, respectively. As compared to the existing NMS algorithm, the proposed design based on the PMMS approach reduces the number of wires in the routing network by 45.5%, and the wirelength of the overall decoder by 17%. The area and power consumption are also reduced by 9.4% and 12%, respectively, as compared to the conventional normalized min-sum (NMS) algorithm.

原文 | English |
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頁（從 - 到） | 1-0 |

頁數 | 2 |

期刊 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |

DOIs | |

出版狀態 | Accepted/In press - 2022 |