Low-power techniques for network security processors

Yi-Ping You; Chun Yen Tseng; Yu Hui Huang; Po Chiun Huang; Ting Ting Hwang; Sheng Yu Hsu

doi:10.1109/ASPDAC.2005.1466188

Low-power techniques for network security processors

Yi-Ping You^*, Chun Yen Tseng, Yu Hui Huang, Po Chiun Huang, Ting Ting Hwang, Sheng Yu Hsu

^*此作品的通信作者

資訊科學與工程研究所

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.

原文	English
主出版物標題	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
頁面	355-360
頁數	6
DOIs	https://doi.org/10.1109/ASPDAC.2005.1466188
出版狀態	Published - 1 12月 2005
事件	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, 中國持續時間: 18 1月 2005 → 21 1月 2005

出版系列

名字	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
卷	1

Conference

Conference	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
國家/地區	中國
城市	Shanghai
期間	18/01/05 → 21/01/05

存取文件

10.1109/ASPDAC.2005.1466188

其它文件與鏈接

Link to publication in Scopus

引用此

You, Y.-P., Tseng, C. Y., Huang, Y. H., Huang, P. C., Hwang, T. T., & Hsu, S. Y. (2005). Low-power techniques for network security processors. 於 Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (頁 355-360). 文章 1466188 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 卷 1). https://doi.org/10.1109/ASPDAC.2005.1466188

@inproceedings{f4de51349c5f44b1b1bcf919f8ce6cc1,

title = "Low-power techniques for network security processors",

abstract = "In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.",

author = "Yi-Ping You and Tseng, {Chun Yen} and Huang, {Yu Hui} and Huang, {Po Chiun} and Hwang, {Ting Ting} and Hsu, {Sheng Yu}",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/ASPDAC.2005.1466188",

language = "English",

isbn = "0780387368",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "355--360",

booktitle = "Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005",

note = "2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 ; Conference date: 18-01-2005 Through 21-01-2005",

}

You, Y-P, Tseng, CY, Huang, YH, Huang, PC, Hwang, TT & Hsu, SY 2005, Low-power techniques for network security processors. 於 Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466188, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 卷 1, 頁 355-360, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, 中國, 18/01/05. https://doi.org/10.1109/ASPDAC.2005.1466188

TY - GEN

T1 - Low-power techniques for network security processors

AU - You, Yi-Ping

AU - Tseng, Chun Yen

AU - Huang, Yu Hui

AU - Huang, Po Chiun

AU - Hwang, Ting Ting

AU - Hsu, Sheng Yu

PY - 2005/12/1

Y1 - 2005/12/1

N2 - In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.

AB - In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.

UR - http://www.scopus.com/inward/record.url?scp=84861450005&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2005.1466188

DO - 10.1109/ASPDAC.2005.1466188

M3 - Conference contribution

AN - SCOPUS:84861450005

SN - 0780387368

SN - 9780780387362

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 355

EP - 360

BT - Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005

T2 - 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005

Y2 - 18 January 2005 through 21 January 2005

ER -

Low-power techniques for network security processors

摘要

出版系列

Conference

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指紋

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