Low-power techniques for network security processors

Yi-Ping You*, Chun Yen Tseng, Yu Hui Huang, Po Chiun Huang, Ting Ting Hwang, Sheng Yu Hsu

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.

原文English
主出版物標題Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
頁面355-360
頁數6
DOIs
出版狀態Published - 1 12月 2005
事件2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
持續時間: 18 1月 200521 1月 2005

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
1

Conference

Conference2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
國家/地區China
城市Shanghai
期間18/01/0521/01/05

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