Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash

Shantanu Rajwade*, Wing Kei Yu, Sarah Xu, Tuo-Hung Hou, G. Edward Suh, Edwin Kan

*此作品的通信作者

    研究成果: Conference contribution同行評審

    4 引文 斯高帕斯(Scopus)

    摘要

    This paper presents a new nonvolatile SRAM design that incorporates low-voltage nanocrystal PMOS Flash transistors. The design enables global store, restore and erase operations with negligible penalty on regular SRAM operation. Store/erase operations also do not consume much power even considering charge pump circuits. Circuit simulations based on experimental I-V characteristics demonstrate that 10 s store/erase operation at 6 Vis sufficient for correct restoration of the stored bit even under reasonable process variation.

    原文English
    主出版物標題Proceedings - IEEE International SOC Conference, SOCC 2010
    頁面461-466
    頁數6
    DOIs
    出版狀態Published - 1 12月 2010
    事件23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States
    持續時間: 27 9月 201029 9月 2010

    出版系列

    名字Proceedings - IEEE International SOC Conference, SOCC 2010

    Conference

    Conference23rd IEEE International SOC Conference, SOCC 2010
    國家/地區United States
    城市Las Vegas, NV
    期間27/09/1029/09/10

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