摘要
The architecture design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency. Design application for IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6mW when operates at 2 V.
原文 | English |
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頁(從 - 到) | 231-234 |
頁數 | 4 |
期刊 | International Symposium on VLSI Technology, Systems, and Applications, Proceedings |
DOIs | |
出版狀態 | Published - 1 1月 1999 |
事件 | Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan 持續時間: 7 6月 1999 → 10 6月 1999 |