Low-power multirate architecture for if digital frequency down converter

Shyh-Jye Jou; Shou Yang Wu; Chorng Kuang Wang

doi:10.1109/82.735360

Low-power multirate architecture for if digital frequency down converter

Shyh-Jye Jou^*, Shou Yang Wu, Chorng Kuang Wang

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摘要

In this paper, a novel low-power multirate architecture for an IF digital frequency downconversion process is presented. The architecture design is the combination of 4-11 oversampling technique and multistage interpolated finite impulse response (IFIR) filter design based on multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational freque.cy. The design example shows that it consumes only 24% power of direct implementation while occupying 26% less area.

原文	English
頁（從 - 到）	1487-1494
頁數	8
期刊	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
卷	45
發行號	11
DOIs	https://doi.org/10.1109/82.735360
出版狀態	Published - 1 12月 1998

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Low-power multirate architecture for if digital frequency down converter

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