In this paper, a novel low-power multirate architecture for an IF digital frequency downconversion process is presented. The architecture design is the combination of 4-11 oversampling technique and multistage interpolated finite impulse response (IFIR) filter design based on multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational freque.cy. The design example shows that it consumes only 24% power of direct implementation while occupying 26% less area.
|頁（從 - 到）||1487-1494|
|期刊||IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing|
|出版狀態||Published - 1 12月 1998|