Low-power memory device with NiSi2 nanocrystals embedded in silicon dioxide layer

P. H. Yeh; C. H. Yu; L. J. Chen; H. H. Wu; Po-Tsun Liu; T. C. Chang

doi:10.1063/1.2126150

Low-power memory device with NiSi₂ nanocrystals embedded in silicon dioxide layer

P. H. Yeh^*, C. H. Yu, L. J. Chen, H. H. Wu, Po-Tsun Liu, T. C. Chang

^*此作品的通信作者

光電工程學系

研究成果: Article › 同行評審

38 引文斯高帕斯（Scopus）

摘要

A metal-oxide-semiconductor structure with NiSi2 nanocrystals embedded in the SiO2 layer has been fabricated. A pronounced capacitance-voltage hysteresis was observed with a memory window of 1 V under the 2 V programming voltage. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry.

原文	English
文章編號	193504
頁（從 - 到）	1-3
頁數	3
期刊	Applied Physics Letters
卷	87
發行號	19
DOIs	https://doi.org/10.1063/1.2126150
出版狀態	Published - 7 11月 2005

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10.1063/1.2126150

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title = "Low-power memory device with NiSi2 nanocrystals embedded in silicon dioxide layer",

abstract = "A metal-oxide-semiconductor structure with NiSi2 nanocrystals embedded in the SiO2 layer has been fabricated. A pronounced capacitance-voltage hysteresis was observed with a memory window of 1 V under the 2 V programming voltage. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry.",

author = "Yeh, {P. H.} and Yu, {C. H.} and Chen, {L. J.} and Wu, {H. H.} and Po-Tsun Liu and Chang, {T. C.}",

year = "2005",

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doi = "10.1063/1.2126150",

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AU - Yeh, P. H.

AU - Yu, C. H.

AU - Chen, L. J.

AU - Wu, H. H.

AU - Liu, Po-Tsun

AU - Chang, T. C.

PY - 2005/11/7

Y1 - 2005/11/7

N2 - A metal-oxide-semiconductor structure with NiSi2 nanocrystals embedded in the SiO2 layer has been fabricated. A pronounced capacitance-voltage hysteresis was observed with a memory window of 1 V under the 2 V programming voltage. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry.

AB - A metal-oxide-semiconductor structure with NiSi2 nanocrystals embedded in the SiO2 layer has been fabricated. A pronounced capacitance-voltage hysteresis was observed with a memory window of 1 V under the 2 V programming voltage. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry.

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U2 - 10.1063/1.2126150

DO - 10.1063/1.2126150

M3 - Article

AN - SCOPUS:27644467439

SN - 0003-6951

VL - 87

SP - 1

EP - 3

JO - Applied Physics Letters

JF - Applied Physics Letters

IS - 19

M1 - 193504

ER -

Low-power memory device with NiSi2 nanocrystals embedded in silicon dioxide layer

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Low-power memory device with NiSi₂ nanocrystals embedded in silicon dioxide layer