TY - JOUR
T1 - Low-power high-speed smart sensor design for space exploration missions
AU - Fang, Wai-Chi
PY - 2000
Y1 - 2000
N2 - A low-power high-speed smart sensor system based on a large format active pixel sensor (APS) integrated with a programmable neural processor for space exploration missions is presented. The concept of building an advanced smart sensing system is demonstrated by a system-level microchip design that is composed with an APS sensor, a programmable neural processor, and an embedded microprocessor in a SOI CMOS technology. This ultra-fast smart sensor system-on-a-chip design mimics what is inherent in biological vision systems. Moreover, it is programmable and capable of performing ultra-fast machine vision processing in all levels such as image acquisition, image fusion, image analysis, scene interpretation, and control functions. The system provides about one tera-operation-per-second computing power which is a two order-of-magnitude increase over that of state-of-the-art microcomputers. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation.
AB - A low-power high-speed smart sensor system based on a large format active pixel sensor (APS) integrated with a programmable neural processor for space exploration missions is presented. The concept of building an advanced smart sensing system is demonstrated by a system-level microchip design that is composed with an APS sensor, a programmable neural processor, and an embedded microprocessor in a SOI CMOS technology. This ultra-fast smart sensor system-on-a-chip design mimics what is inherent in biological vision systems. Moreover, it is programmable and capable of performing ultra-fast machine vision processing in all levels such as image acquisition, image fusion, image analysis, scene interpretation, and control functions. The system provides about one tera-operation-per-second computing power which is a two order-of-magnitude increase over that of state-of-the-art microcomputers. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation.
UR - http://www.scopus.com/inward/record.url?scp=0033871275&partnerID=8YFLogxK
U2 - 10.1016/S0094-5765(99)00205-2
DO - 10.1016/S0094-5765(99)00205-2
M3 - Conference article
AN - SCOPUS:0033871275
SN - 0094-5765
VL - 46
SP - 241
EP - 250
JO - Acta Astronautica
JF - Acta Astronautica
IS - 2
T2 - The 2nd IAA International Symposium on Small Satellites for Earth Observation
Y2 - 12 April 1999 through 16 April 1999
ER -