Low-power globally asynchronous locally synchronous design using self-timed circuit technology

Shyh-Jye Jou; I. Yao Chuang

doi:10.1109/ISCAS.1997.621497

Low-power globally asynchronous locally synchronous design using self-timed circuit technology

Shyh-Jye Jou^*, I. Yao Chuang

^*此作品的通信作者

電子研究所

研究成果: Conference article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

In this paper, an efficient implementation of self-timed circuits whose hardware and control signals are significantly reduced is first proposed. By applying Globally Asynchronous Locally Synchronous (GALS) design techniques, the hardware overhead is further reduced. GALS and synchronous version of 8-bit fully pipelined array multipliers are implemented for comparisons. The results show that GALS version has smaller peak current, less power consumption under variable workload with small hardware overhead as compared to synchronous version.

原文	English
文章編號	5745106
頁（從 - 到）	1808-1811
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	3
DOIs	https://doi.org/10.1109/ISCAS.1997.621497
出版狀態	Published - 1 1月 1997
事件	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong 持續時間: 9 6月 1997 → 12 6月 1997

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10.1109/ISCAS.1997.621497

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abstract = "In this paper, an efficient implementation of self-timed circuits whose hardware and control signals are significantly reduced is first proposed. By applying Globally Asynchronous Locally Synchronous (GALS) design techniques, the hardware overhead is further reduced. GALS and synchronous version of 8-bit fully pipelined array multipliers are implemented for comparisons. The results show that GALS version has smaller peak current, less power consumption under variable workload with small hardware overhead as compared to synchronous version.",

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AU - Jou, Shyh-Jye

AU - Chuang, I. Yao

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AB - In this paper, an efficient implementation of self-timed circuits whose hardware and control signals are significantly reduced is first proposed. By applying Globally Asynchronous Locally Synchronous (GALS) design techniques, the hardware overhead is further reduced. GALS and synchronous version of 8-bit fully pipelined array multipliers are implemented for comparisons. The results show that GALS version has smaller peak current, less power consumption under variable workload with small hardware overhead as compared to synchronous version.

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Low-power globally asynchronous locally synchronous design using self-timed circuit technology

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