TY - JOUR
T1 - Low-power globally asynchronous locally synchronous design using self-timed circuit technology
AU - Jou, Shyh-Jye
AU - Chuang, I. Yao
PY - 1997/1/1
Y1 - 1997/1/1
N2 - In this paper, an efficient implementation of self-timed circuits whose hardware and control signals are significantly reduced is first proposed. By applying Globally Asynchronous Locally Synchronous (GALS) design techniques, the hardware overhead is further reduced. GALS and synchronous version of 8-bit fully pipelined array multipliers are implemented for comparisons. The results show that GALS version has smaller peak current, less power consumption under variable workload with small hardware overhead as compared to synchronous version.
AB - In this paper, an efficient implementation of self-timed circuits whose hardware and control signals are significantly reduced is first proposed. By applying Globally Asynchronous Locally Synchronous (GALS) design techniques, the hardware overhead is further reduced. GALS and synchronous version of 8-bit fully pipelined array multipliers are implemented for comparisons. The results show that GALS version has smaller peak current, less power consumption under variable workload with small hardware overhead as compared to synchronous version.
UR - http://www.scopus.com/inward/record.url?scp=0030719807&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.1997.621497
DO - 10.1109/ISCAS.1997.621497
M3 - Conference article
AN - SCOPUS:0030719807
SN - 0271-4310
VL - 3
SP - 1808
EP - 1811
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 5745106
T2 - Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)
Y2 - 9 June 1997 through 12 June 1997
ER -