Applying clock gating in three dimensional integrated circuits (3D ICs) is essential for reducing power consumption and improving circuit reliability. However, the previous works only present algorithms for 3D clock tree synthesis. None of them address gated clock tree in 3D ICs for dynamic power reduction. In this paper, we propose the first problem formulation in the literature for 3D gated clock network optimization. We consider both flip-flop switching activities and the timing constraint of enable signal paths at clock gating cells when constructing topological gated clock trees. Based on the topological gated clock trees, a zero-skew 3D clock routing tree is then generated. Experimental results show that, compared with conventional 3D clock tree synthesis, the proposed 3D gated clock tree synthesis can achieve much less power consumption with similar number of TSVs and clock tree wirelength.