Low-power gated clock tree optimization for three-dimensional integrated circuits

Yu Chuan Chen, Chih Cheng Hsu, Po-Hung Lin

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

Applying clock gating in three dimensional integrated circuits (3D ICs) is essential for reducing power consumption and improving circuit reliability. However, the previous works only present algorithms for 3D clock tree synthesis. None of them address gated clock tree in 3D ICs for dynamic power reduction. In this paper, we propose the first problem formulation in the literature for 3D gated clock network optimization. We consider both flip-flop switching activities and the timing constraint of enable signal paths at clock gating cells when constructing topological gated clock trees. Based on the topological gated clock trees, a zero-skew 3D clock routing tree is then generated. Experimental results show that, compared with conventional 3D clock tree synthesis, the proposed 3D gated clock tree synthesis can achieve much less power consumption with similar number of TSVs and clock tree wirelength.

原文English
主出版物標題2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781479962754
DOIs
出版狀態Published - 28 五月 2015
事件2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan
持續時間: 27 四月 201529 四月 2015

出版系列

名字2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Conference

Conference2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
國家/地區Taiwan
城市Hsinchu
期間27/04/1529/04/15

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