Low-power digital CDMA receiver

Ja Sheng Liu, I. Hsin Chen, Yi Chen Tai, Shyh-Jye Jou

研究成果: Conference contribution同行評審

摘要

The advanced design tasks for a digital CDMA receiver are presented in this report. A biased number system and architecture are used to reduce the switching activity to reduce power consumption. A carry-save adder tree is used to speed up the summation of 127 data (3 bits) in the synchronization and date extraction process. Verilog HDL is used to describe this system and the design compiler of Synopsys is used to synthesize our design. Design results show that it can work at 155 MHz (chip rate) with 9913 gate counts by using the Compass 0.35 μm CMOS cell library.

原文English
主出版物標題Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
發行者Institute of Electrical and Electronics Engineers Inc.
頁面581-582
頁數2
ISBN(電子)0780376595
DOIs
出版狀態Published - 1 1月 2003
事件Asia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
持續時間: 21 1月 200324 1月 2003

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2003-January

Conference

ConferenceAsia and South Pacific Design Automation Conference, ASP-DAC 2003
國家/地區Japan
城市Kitakyushu
期間21/01/0324/01/03

指紋

深入研究「Low-power digital CDMA receiver」主題。共同形成了獨特的指紋。

引用此