@inproceedings{108211809503410394c91b18421cc2d1,
title = "Low-power digital CDMA receiver",
abstract = "The advanced design tasks for a digital CDMA receiver are presented in this report. A biased number system and architecture are used to reduce the switching activity to reduce power consumption. A carry-save adder tree is used to speed up the summation of 127 data (3 bits) in the synchronization and date extraction process. Verilog HDL is used to describe this system and the design compiler of Synopsys is used to synthesize our design. Design results show that it can work at 155 MHz (chip rate) with 9913 gate counts by using the Compass 0.35 μm CMOS cell library.",
author = "Liu, {Ja Sheng} and Chen, {I. Hsin} and Tai, {Yi Chen} and Shyh-Jye Jou",
year = "2003",
month = jan,
day = "1",
doi = "10.1109/ASPDAC.2003.1195088",
language = "English",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "581--582",
booktitle = "Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference",
address = "美國",
note = "Asia and South Pacific Design Automation Conference, ASP-DAC 2003 ; Conference date: 21-01-2003 Through 24-01-2003",
}