Low power device technology with SiGe channel, HfSiON, and poly-Si gate

Howard C.H. Wang*, Shang Jr Chen, Ming Fang Wang, Pang Yen Tsai, Ching Wei Tsai, Ta Wei Wang, Steve M. Ting, Tuo-Hung Hou, Peng Soon Lim, Huan Just Lin, Ying Jin, Hun Jan Tao, Shih Chang Chen, Carlos H. Diaz, Mong Song Liang, Chen-Ming Hu

*此作品的通信作者

研究成果: Conference contribution同行評審

20 引文 斯高帕斯(Scopus)

摘要

We report solutions to the formidable challenges posed by integrating a HfSiON dielectric with a poly-Si gate for low-power device technology. A 1.5 nm EOT HfSiON is demonstrated with mobility comparable to SiO 2 and 3 orders of magnitude leakage reduction. A novel boron delta-doped strained-SiGe channel points a way out of the high threshold voltage problem associated with Fermi-pinning at the high-k/poly-Si interface and ameliorates short-channel effects in PMOS devices. In addition, a 20% hole mobility enhancement and 15% I on -I off characteristics improvement are achieved owing to the compressive SiGe channel. NMOS PBTI lifetime of 35 years, and PMOS NBTI and NMOS hot carrier lifetimes of more than 1000 years are demonstrated at 1.2 V.

原文English
主出版物標題IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST
發行者IEEE
頁面161-164
頁數4
ISBN(列印)0-7803-8684-1
DOIs
出版狀態Published - 1 12月 2004
事件IEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States
持續時間: 13 12月 200415 12月 2004

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
發行者Institute of Electrical and Electronics Engineers Inc.
ISSN(列印)0163-1918

Conference

ConferenceIEEE International Electron Devices Meeting, 2004 IEDM
國家/地區United States
城市San Francisco, CA
期間13/12/0415/12/04

指紋

深入研究「Low power device technology with SiGe channel, HfSiON, and poly-Si gate」主題。共同形成了獨特的指紋。

引用此